3 ms·
Ah, so the idea is to have 64 parallel bits coming in at 6 Gbits/s, along with a slower clock that you multiply up to 6 GHz and use to sample the inputs? That w
by mechagodzilla 12y ago
Ah, so the idea is to have 64 parallel bits coming in at 6 Gbits/s, along with a slower clock that you multiply up to 6 GHz and use to sample the inputs? That will be quite tricky to get working 1) without any analog signal conditioning on the inputs (or outputs), and 2) without inter-bit skew making it impossible to meet timing on your inputs. Best of luck to you, but the interface alone sounds likely to be problematic.
- trsohmers 12y agoThat's the basic idea, but we can run it at 3GHz if we do DDR, or 1.5GHz doing QDR. There is some extra magic there which I don't want to talk publicly about just yet ;) The biggest problem (even with our solutions for skew and crosstalk) is just the number of pins/traces on the board, but that's not unsolvable... nothing a ~10 layer PCB can't solve.