The superscalar design means Load/Store unit can operate independently from FMA and DMA units, i.e. FMA operation on register operands will not interfere with o

The superscalar design means Load/Store unit can operate independently from FMA and DMA units, i.e. FMA operation on register operands will not interfere with other operations elsewhere on the chip. Synchronization should be handled in a dataflow-driven program design. Any sort of mutex/semaphore/etc. will have to be software defined or interrupt-driven. In regards to neighboring node being memory mapped... are you asking about another compute chip or another node (with the 16 compute chips + GaMMU)? All of the compute chips in a grid are part of the same flat global memory map, and have DMA capabilities between each other. Once you get out of the compute grid (that is managed by the GaMMU), then that is a separate memory space, but can be accessed through some other layer through something like MPI, for instance.