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I discredit most people who continue the RISC/CISC debate to this day (As Intel forfeited in ~2006... all modern x86 processors are actually RISC processors. Th

I discredit most people who continue the RISC/CISC debate to this day (As Intel forfeited in ~2006... all modern x86 processors are actually RISC processors. They are RISC at the lowest level, and just decode x86 instruction and translate them into Intel RISC microcode). Then again, I don't think most popular "RISC" CPUs are very RISC like (Does that make me a RISC hipster?). While making things general purpose, there is no reason for ARM processors to be OoO, do branch prediction/speculative execution, or any more of these crazy things... it reduces efficiency in the long run. Take a look at this for instance: http://chip-architect.com/news/2013_core_sizes_768.jpg http://chip-architect.com/news/2013_core_sizes_768.jpg ... an AMD CPU and ARM chip are virtually the same size at the same process node. I find it insane that one of our cores is a bit less than 1/5th of the size of a cortex A7, and can do more FLOPs than it. Then again, we have focused on doing that, but still.

nkurz 12y ago
Your .1 mm^2 was without memory, right? I don't know the exact numbers, but to be fair, the ratio does become somewhat closer when you discount the area on the A7 used for memory: http://www.arm.com/images/Single_Cortex-A7_core_layout_image.jpg http://www.arm.com/images/Single_Cortex-A7_core_layout_image...
- trsohmers 12y ago
  That is correct, but even with memory we should only be around .2mm^2 to .3mm^2, while having 4x the SRAM as the Cortex-A7.
Taniwha 12y ago
I think it's fair, despite long-time predjudices - to think of the x86 architecture to be midway between RISC and CISC - most instructions (push/etc being the notable exception) make a single memory reference and no addressing mode does a memory indirect or has addressing side effects (auto incs/etc)- that means that instructions are retryable (don't ever need to be able to be restarted in the middle after a page fault) with a single dcache/TLB port

nkurz 12y ago

Your .1 mm^2 was without memory, right? I don't know the exact numbers, but to be fair, the ratio does become somewhat closer when you discount the area on the A7 used for memory: http://www.arm.com/images/Single_Cortex-A7_core_layout_image.jpg http://www.arm.com/images/Single_Cortex-A7_core_layout_image...

trsohmers 12y ago
That is correct, but even with memory we should only be around .2mm^2 to .3mm^2, while having 4x the SRAM as the Cortex-A7.

Taniwha 12y ago

I think it's fair, despite long-time predjudices - to think of the x86 architecture to be midway between RISC and CISC - most instructions (push/etc being the notable exception) make a single memory reference and no addressing mode does a memory indirect or has addressing side effects (auto incs/etc)- that means that instructions are retryable (don't ever need to be able to be restarted in the middle after a page fault) with a single dcache/TLB port