3 ms·

Thanks for that... didn't notice that we had a repeated section (I just updated it with the proper text for that section) As for comparison to the Phi... it is

Thanks for that... didn't notice that we had a repeated section (I just updated it with the proper text for that section) As for comparison to the Phi... it is the fact that our actual core size (and thus the whole chip) is MUCH smaller. The Phi's cores are actually based on the original Pentium architecture (they are just downsized P54Cs) with added AVX instructions. Contrary to popular belief, they are not full x86-64 cores. Intel has not released the official die size for the Phi, but has said it is about ~5 billion transistors (at a 22nm process), and independent "guesstimates" have pegged the die at 600-700mm2 (there is one place that says 350mm2, but that is false). For the top of the line 61 core Xeon Phi, it uses 300W, with a theoretical peak performance of 1.2TFLOP of double precision performance. That gets you to about 4GFLOP/Watt. In comparison, our entire will be under 100 million gates, with each core (excluding memory) being around 100k gates. At a 28nm process, our core size (without memory) is a little under 0.1mm2. Our theoretical peak performance per compute chip is 256 GFLOPs double precision, while it should be using around 3 Watts, giving us a performance per watt ratio of ~85GFLOPs/Watt. Intel has even said that their next generation Xeon Phi, made at their 14nm process, will be at 14 to 16GFLOPs/Watt. At SC14 last week, they made a soft announcement for the following generation at 10nm process will be in the ~2018 timeframe, and that is estimated at only being around 25GFLOPs/Watt. The bottom line is Intel is just following Moore's law, and is sticking to big and complex systems, which while retaining legacy compatibility, kill you when it comes to efficiency.

nkurz 12y ago
Interesting, and a great answer. The usual estimates I've seen put the power efficiency overhead of the legacy x86 layer to be small enough to not be a major factor (http://research.cs.wisc.edu/vertical/papers/2013/hpca13-isa-power-struggles.pdf http://research.cs.wisc.edu/vertical/papers/2013/hpca13-isa-...). But I suppose as you shrink the core smaller and smaller, that small mostly-fixed difference becomes a greater and greater part of the total power budget.
- trsohmers 12y ago
  I discredit most people who continue the RISC/CISC debate to this day (As Intel forfeited in ~2006... all modern x86 processors are actually RISC processors. They are RISC at the lowest level, and just decode x86 instruction and translate them into Intel RISC microcode). Then again, I don't think most popular "RISC" CPUs are very RISC like (Does that make me a RISC hipster?). While making things general purpose, there is no reason for ARM processors to be OoO, do branch prediction/speculative execution, or any more of these crazy things... it reduces efficiency in the long run. Take a look at this for instance: http://chip-architect.com/news/2013_core_sizes_768.jpg http://chip-architect.com/news/2013_core_sizes_768.jpg ... an AMD CPU and ARM chip are virtually the same size at the same process node. I find it insane that one of our cores is a bit less than 1/5th of the size of a cortex A7, and can do more FLOPs than it. Then again, we have focused on doing that, but still.
  - nkurz 12y ago
    Your .1 mm^2 was without memory, right? I don't know the exact numbers, but to be fair, the ratio does become somewhat closer when you discount the area on the A7 used for memory: http://www.arm.com/images/Single_Cortex-A7_core_layout_image.jpg http://www.arm.com/images/Single_Cortex-A7_core_layout_image...
    - trsohmers 12y ago
      That is correct, but even with memory we should only be around .2mm^2 to .3mm^2, while having 4x the SRAM as the Cortex-A7.
  - Taniwha 12y ago
    I think it's fair, despite long-time predjudices - to think of the x86 architecture to be midway between RISC and CISC - most instructions (push/etc being the notable exception) make a single memory reference and no addressing mode does a memory indirect or has addressing side effects (auto incs/etc)- that means that instructions are retryable (don't ever need to be able to be restarted in the middle after a page fault) with a single dcache/TLB port
m_mueller 12y ago
Intel's insistence on x86 and dragging old designs around just isn't sustainable in the long run, especially once silicon gets to its absolute physical limits and Intel looses its traditional process technology advantage for a while (until a new material is introduced). Knight's Landing may be a temporary reverse to the killer micro order, but I give a higher chance to IBM+NVIDIA winning the next round, maybe followed by an architecture like yours.

nkurz 12y ago

Interesting, and a great answer. The usual estimates I've seen put the power efficiency overhead of the legacy x86 layer to be small enough to not be a major factor (http://research.cs.wisc.edu/vertical/papers/2013/hpca13-isa-power-struggles.pdf http://research.cs.wisc.edu/vertical/papers/2013/hpca13-isa-...). But I suppose as you shrink the core smaller and smaller, that small mostly-fixed difference becomes a greater and greater part of the total power budget.

trsohmers 12y ago
I discredit most people who continue the RISC/CISC debate to this day (As Intel forfeited in ~2006... all modern x86 processors are actually RISC processors. They are RISC at the lowest level, and just decode x86 instruction and translate them into Intel RISC microcode). Then again, I don't think most popular "RISC" CPUs are very RISC like (Does that make me a RISC hipster?). While making things general purpose, there is no reason for ARM processors to be OoO, do branch prediction/speculative execution, or any more of these crazy things... it reduces efficiency in the long run. Take a look at this for instance: http://chip-architect.com/news/2013_core_sizes_768.jpg http://chip-architect.com/news/2013_core_sizes_768.jpg ... an AMD CPU and ARM chip are virtually the same size at the same process node. I find it insane that one of our cores is a bit less than 1/5th of the size of a cortex A7, and can do more FLOPs than it. Then again, we have focused on doing that, but still.
- nkurz 12y ago
  Your .1 mm^2 was without memory, right? I don't know the exact numbers, but to be fair, the ratio does become somewhat closer when you discount the area on the A7 used for memory: http://www.arm.com/images/Single_Cortex-A7_core_layout_image.jpg http://www.arm.com/images/Single_Cortex-A7_core_layout_image...
  - trsohmers 12y ago
    That is correct, but even with memory we should only be around .2mm^2 to .3mm^2, while having 4x the SRAM as the Cortex-A7.
- Taniwha 12y ago
  I think it's fair, despite long-time predjudices - to think of the x86 architecture to be midway between RISC and CISC - most instructions (push/etc being the notable exception) make a single memory reference and no addressing mode does a memory indirect or has addressing side effects (auto incs/etc)- that means that instructions are retryable (don't ever need to be able to be restarted in the middle after a page fault) with a single dcache/TLB port

m_mueller 12y ago

Intel's insistence on x86 and dragging old designs around just isn't sustainable in the long run, especially once silicon gets to its absolute physical limits and Intel looses its traditional process technology advantage for a while (until a new material is introduced). Knight's Landing may be a temporary reverse to the killer micro order, but I give a higher chance to IBM+NVIDIA winning the next round, maybe followed by an architecture like yours.