I should also point out that it isn't just a bunch of ALUs or FPUs connected by a network... each core has it's own full execution logic, making each core a ful

I should also point out that it isn't just a bunch of ALUs or FPUs connected by a network... each core has it's own full execution logic, making each core a full 5-stage superscalar RISC core that can independently operate on its own instruction and own piece of data.