4 ms·

My first thought was how this compares to Adapteva's Epiphany architecture (best known for it's use in their crowd-funded Parallela boards), so I was happy to s

My first thought was how this compares to Adapteva's Epiphany architecture (best known for it's use in their crowd-funded Parallela boards), so I was happy to see this project was inspired by that one. Andreas Olofsson from Adapteva has tweeted often about how difficult it is to get funding as a silicon start up, though. I think the statement "it's a tough sell" will prove to be a colossal understatement. But these are impressive kids and it's a great concept - I wish them luck.

trsohmers 12y ago
I was working on the Parallela boards for a long time... but there are fundamental flaws in the architecture (missing instructions, it is only 32 bit, not IEEE754-2008 compliant, etc) that makes the Epiphany architecture not really suitable for the markets we are trying to address. When we decided to go out and make our own, we knew there was going to be a lot of difficulties, but the idea is that if we are going to do a startup and give it our all, why not try to do something big? The fact that we are using mostly open source tools for our development (such as Chisel: chisel.eecs.berkeley.edu), our development time has decreased and productivity has had a huge boost compared to if we were just writing in Verilog. We also made the decision to not use off the shelf IP, which while difficult to verify, we think we make a much better system. Compare this to the Epiphany implementations, which while having a custom ISA and basic core components, used off the shelf ARM interconnect, off the shelf ARM memory compiler, and many other things that were used to minimize development time and verification. While this is a bit more difficult upfront, since we are keeping our components very simple, our verification is no where near as complex as a "normal" processor. Plus we don't have to pay $500k-$1m+ in upfront licensing fees.

trsohmers 12y ago

I was working on the Parallela boards for a long time... but there are fundamental flaws in the architecture (missing instructions, it is only 32 bit, not IEEE754-2008 compliant, etc) that makes the Epiphany architecture not really suitable for the markets we are trying to address. When we decided to go out and make our own, we knew there was going to be a lot of difficulties, but the idea is that if we are going to do a startup and give it our all, why not try to do something big? The fact that we are using mostly open source tools for our development (such as Chisel: chisel.eecs.berkeley.edu), our development time has decreased and productivity has had a huge boost compared to if we were just writing in Verilog. We also made the decision to not use off the shelf IP, which while difficult to verify, we think we make a much better system. Compare this to the Epiphany implementations, which while having a custom ISA and basic core components, used off the shelf ARM interconnect, off the shelf ARM memory compiler, and many other things that were used to minimize development time and verification. While this is a bit more difficult upfront, since we are keeping our components very simple, our verification is no where near as complex as a "normal" processor. Plus we don't have to pay $500k-$1m+ in upfront licensing fees.