3 ms·

The article was unclear in your open source plans. Will you be opening your hdl, and under what license?

by asb 12y ago

trsohmers 12y ago
So our current initial plans are to open source the ISA through the Open Compute Project (http://opencompute.org http://opencompute.org), using their reciprocal license. The HPC group within OCP that I co-lead has plans for HDL and RTL level submissions, but we are not sure what the timeframe or what would be included from REX (yet). The business case for open sourcing the ISA is that we want others to be making compatible chips. As a small startup with a new architecture, it would be GREAT if others were to make competing chips, as it would only further the architecture and software ecosystem, making it more competitive with the existing market incumbents. To us, our floating point unit is our "secret sauce", but as an open source enthusiast, I don't want that to be locked up forever. My general idea right now is that we want to be able to tape out our first chip (at least the prototypes for it), and will open source the HDL for the non "secret sauce" parts of it. As we get onto further generations, I do want to open source the full design of our previous chips for free/open use.
- asb 12y ago
  Thanks for the answer. Another quick question. One of the limitations of parallela is the offchip memory bandwidth. Will you be integrating a third party phy?
  - trsohmers 12y ago
    Our chip-to-chip bandwidth is currently 48GB/s per parallel interface, and we have 8 of those per chip (2 per side), giving us an aggregate bandwidth of 384GB/s. The Epiphany 4's interfaces are 1.5GB/s serial (12.5Gb serdes), and there are 4 of those per chip, giving you an aggregate bandwidth of 6GB/s. If you can spend a bit more power (or wait for 14/16nm process), we think it is possible to double that to 96GB/s per interface. Using some more exotic methods (which are purely in an idea stage right now, and not tested, are are a couple years away at best), we think it is possible to get that up to 128GB/s per interface.
    - mechagodzilla 12y ago
      Can you provide some more details on your parallel interface? As an ASIC designer, these numbers sound extremely fishy for a non-serdes interface. A 128-bit parallel interface (which is a lot of pins, especially if you need 8 links) would need to be running at 3 GHz, for instance, to hit that. Is it differential/single-ended? Source-synchronous? How big of a package are you planning?
      - trsohmers 12y ago
        (Copied from another comment on this page): Relevant paper (by Intel Research, actually)... there are quite a few differences (we are keeping it a lot simpler on the tx and rx ends, but that is some of our secret sauce... I can talk about it offline if you are really interested) http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=648778.. http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=648778....
        ajb 12y ago
        FYI, That link doesn't work, but the one you posted here: https://news.ycombinator.com/item?id=8659653 https://news.ycombinator.com/item?id=8659653 does.
      - deleted 12y ago
        [deleted]

The article was unclear in your open source plans. Will you be opening your hdl, and under what license?

by asb 12y ago

The article was unclear in your open source plans. Will you be opening your hdl, and under what license?

So our current initial plans are to open source the ISA through the Open Compute Project (http://opencompute.org http://opencompute.org), using their reciprocal license. The HPC group within OCP that I co-lead has plans for HDL and RTL level submissions, but we are not sure what the timeframe or what would be included from REX (yet). The business case for open sourcing the ISA is that we want others to be making compatible chips. As a small startup with a new architecture, it would be GREAT if others were to make competing chips, as it would only further the architecture and software ecosystem, making it more competitive with the existing market incumbents. To us, our floating point unit is our "secret sauce", but as an open source enthusiast, I don't want that to be locked up forever. My general idea right now is that we want to be able to tape out our first chip (at least the prototypes for it), and will open source the HDL for the non "secret sauce" parts of it. As we get onto further generations, I do want to open source the full design of our previous chips for free/open use.

asb 12y ago
Thanks for the answer. Another quick question. One of the limitations of parallela is the offchip memory bandwidth. Will you be integrating a third party phy?
- trsohmers 12y ago
  Our chip-to-chip bandwidth is currently 48GB/s per parallel interface, and we have 8 of those per chip (2 per side), giving us an aggregate bandwidth of 384GB/s. The Epiphany 4's interfaces are 1.5GB/s serial (12.5Gb serdes), and there are 4 of those per chip, giving you an aggregate bandwidth of 6GB/s. If you can spend a bit more power (or wait for 14/16nm process), we think it is possible to double that to 96GB/s per interface. Using some more exotic methods (which are purely in an idea stage right now, and not tested, are are a couple years away at best), we think it is possible to get that up to 128GB/s per interface.
  - mechagodzilla 12y ago
    Can you provide some more details on your parallel interface? As an ASIC designer, these numbers sound extremely fishy for a non-serdes interface. A 128-bit parallel interface (which is a lot of pins, especially if you need 8 links) would need to be running at 3 GHz, for instance, to hit that. Is it differential/single-ended? Source-synchronous? How big of a package are you planning?
    - trsohmers 12y ago
      (Copied from another comment on this page): Relevant paper (by Intel Research, actually)... there are quite a few differences (we are keeping it a lot simpler on the tx and rx ends, but that is some of our secret sauce... I can talk about it offline if you are really interested) http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=648778.. http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=648778....
      - ajb 12y ago
        FYI, That link doesn't work, but the one you posted here: https://news.ycombinator.com/item?id=8659653 https://news.ycombinator.com/item?id=8659653 does.
    - deleted 12y ago
      [deleted]