4 ms·

This tripped me up a bit >Local scratchpad memories are physically addressed as part of a flat global address space. So from the programmers perspective each

This tripped me up a bit >Local scratchpad memories are physically addressed as part of a flat global address space. So from the programmers perspective each core will have a block of the address space, I.E.: 0-255, 256-511, 512-767, 768-1023 etc.? Or is there address translation between units? Or if a thread is just built to arbitrarily execute on a unit, it'll have to pre-process its position for name space translation? Also is there a memory locking in local scratchpad? (I maybe reaching).

trsohmers 12y ago
At the physical level, each core would have a 128k block that is ascending, but the idea is that our compilers would abstract that away from the programmer, and allocate memory based on what core needs it, and place it in that core's scratchpad, or as close as possible. The DMA capabilities abstract it when actually accessing memory, as it is just a series of (very simple) comparators that get the request to the write block of memory.
- valarauca1 12y ago
  So the scratchpad isn't so much programmer controlled as just a L1 cache level?
  - trsohmers 12y ago
    I would not call it a cache as it is: 1)Physically addressed 2)Has no complex control logic (TLB, CAMs, additional flags) 3)Us not just simply replicating something higher up in a memory hierarchy A programmer will have full access to be able to handle memory however they want, but we want to be able to build out the tools to allow for a programmer to treat it similarly to an L1 cache (that is part of a shared memory space... that has different access times)
    - valarauca1 12y ago
      Interesting. I look forward to playing around with one.
    - wglb 12y ago
      So the scratchpad memory contains instructions as well as data?
    - trsohmers 12y ago
      @wglb: That is the plan for now. An instruction cache is possible, but we don't see the need to add extra complexity.

trsohmers 12y ago

At the physical level, each core would have a 128k block that is ascending, but the idea is that our compilers would abstract that away from the programmer, and allocate memory based on what core needs it, and place it in that core's scratchpad, or as close as possible. The DMA capabilities abstract it when actually accessing memory, as it is just a series of (very simple) comparators that get the request to the write block of memory.

valarauca1 12y ago
So the scratchpad isn't so much programmer controlled as just a L1 cache level?
- trsohmers 12y ago
  I would not call it a cache as it is: 1)Physically addressed 2)Has no complex control logic (TLB, CAMs, additional flags) 3)Us not just simply replicating something higher up in a memory hierarchy A programmer will have full access to be able to handle memory however they want, but we want to be able to build out the tools to allow for a programmer to treat it similarly to an L1 cache (that is part of a shared memory space... that has different access times)
  - valarauca1 12y ago
    Interesting. I look forward to playing around with one.
  - wglb 12y ago
    So the scratchpad memory contains instructions as well as data?
  - trsohmers 12y ago
    @wglb: That is the plan for now. An instruction cache is possible, but we don't see the need to add extra complexity.