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Impressive for your age. But how is this any different from the millions of identical proposals that never got anywhere? Packing plenty of alus with some sort o

Impressive for your age. But how is this any different from the millions of identical proposals that never got anywhere? Packing plenty of alus with some sort of basic network hasn't really worked out in real life. The first block diagram in the article is so basic it's concerning. Apologies for being critical, I wish you the best.

trsohmers 12y ago
The article is incorrect in saying that the (very simplistic...it's supposed to just show the basic components per core, not how it is actually functioning) diagram for a single core is the whole chip... our chip design has 256 of those cores (So in total, 256 64 bit ALUs and 256 64 bit FPUs). We have a custom mesh network that allows for atomic operations on from any core to any adjacent core, and DMA operations that allow for a read or write to any core's local scratchpad memory from any other scratchpad memory. In comparison to other architectures, we have chose to stick to RISC, instead of some crazy VLIW or very long pipeline scheme. In doing this, we limit compiler complexity while still having very simple/efficient core design, and thus hopefully keeping every core's pipeline full and without hazards. The idea is that we just want to have a bunch of very simple and focused SPMD cores, so that we can have a MIMD/MPMD chip. We are currently fixing the bugs on our single core FPGA demo, and hope to have our full 256 core cycle accurate simulator done by ~January/February. We want to release that (and our currently very early compilers) to the public ASAP.
trsohmers 12y ago
I should also point out that it isn't just a bunch of ALUs or FPUs connected by a network... each core has it's own full execution logic, making each core a full 5-stage superscalar RISC core that can independently operate on its own instruction and own piece of data.

trsohmers 12y ago

The article is incorrect in saying that the (very simplistic...it's supposed to just show the basic components per core, not how it is actually functioning) diagram for a single core is the whole chip... our chip design has 256 of those cores (So in total, 256 64 bit ALUs and 256 64 bit FPUs). We have a custom mesh network that allows for atomic operations on from any core to any adjacent core, and DMA operations that allow for a read or write to any core's local scratchpad memory from any other scratchpad memory. In comparison to other architectures, we have chose to stick to RISC, instead of some crazy VLIW or very long pipeline scheme. In doing this, we limit compiler complexity while still having very simple/efficient core design, and thus hopefully keeping every core's pipeline full and without hazards. The idea is that we just want to have a bunch of very simple and focused SPMD cores, so that we can have a MIMD/MPMD chip. We are currently fixing the bugs on our single core FPGA demo, and hope to have our full 256 core cycle accurate simulator done by ~January/February. We want to release that (and our currently very early compilers) to the public ASAP.

trsohmers 12y ago

I should also point out that it isn't just a bunch of ALUs or FPUs connected by a network... each core has it's own full execution logic, making each core a full 5-stage superscalar RISC core that can independently operate on its own instruction and own piece of data.