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As Click discusses in his Google tech talk (http://www.youtube.com/watch?v=5uljtqyBLxI http://www.youtube.com/watch?v=5uljtqyBLxI) Intel could implement a hardw
by jeremyw 17y ago
As Click discusses in his Google tech talk (http://www.youtube.com/watch?v=5uljtqyBLxI http://www.youtube.com/watch?v=5uljtqyBLxI) Intel could implement a hardware read-barrier and radically change the GC performance picture for commodity systems.
- asciilifeform 17y agoThere are many things CPU designers could do to improve high-level language performance. (See: http://www.loper-os.org/?p=46 http://www.loper-os.org/?p=46) However, they will do none of them. The "we shall build C/C++ machines forever" dogma continues to rule with an iron fist. There "is no market" for high-level-language-friendly silicon, because there is no software for it, because there is no market...
- jeremyw 17y agoActually, there has always been vigorous interaction between OS and chip designers. See VM evolution, performance counters, matrix/vector operations. I think read-barrier support, as a proven technique (see the same video for transactional memory as a functional bust) is on the cusp of acceptance.