Well at the interface level it has to look like memory since it's attached to a memory bus. But that does not mean it looks like a single large DIMM. There is

Well at the interface level it has to look like memory since it's attached to a memory bus. But that does not mean it looks like a single large DIMM. There is no way in the DRAM protocol to delay a transaction while data is read from the flash chips into the buffer, so you need a protocol on top of the simple memory model. "nvDIMMs" on the other hand do look like and are as fast as plain memory. Disadvantage is that they are not big.