3 ms·

Also let's not forget HP said it's possible that memristors will also perform computation, which melds RAM, HDD and CPU into one and makes for a potentially wil

• derefr 12y ago
  If we keep to the implicitly-shared-by-default UMA/NUMA architecture we've been working with so far. I'd imagine a combined compute-memory-storage unit would be mostly hardware-isolated, with something resembling message-passing semantics for cross-core communication. Something more like FPGA cells, or Erlang processes. (With the likely property that you could have pools of these cells that act like plain memory, for other cells to share and manipulate using handles/segment descriptors/whatever.) True, even under this model, you could probably have a virus running "resident" in a core without the OS even being aware of it. Basically, it's be like the MMU was a hypervisor and the OS was just a domU within it, unaware of viral "domains." But those viruses probably wouldn't be able to do much, except waste electricity, because they'd need to either get the IOMMU to allocate them some hardware to do IO, or get the OS (which has such hardware) to agree to do IO on its behalf. (Though now we can get into things like intermittent side-channel attacks, where you can mine bitcoins on one cell for minutes and then only have to get the OS to leak a single packet when you have a (rare) success, which is much simpler than getting a whole stable TCP channel or something.)