4 ms·

Show HN: OpenRISC JavaScript emulator emulates up to 16 cores

43 points by s-macke 12y ago

s-macke 12y ago
Just some technical details: The cores are emulated in one worker thread because shared memory in threads is still not supported by the engines. You can use "htop" to see the cores at work. You can run a multithreaded fractal generator with "mandelpar" too.
- benjamincburns 12y ago
  Is there any performance improvement on multithreaded tasks with SMP enabled?
  - s-macke 12y ago
    Not yet. But when shared memory arrays become available in Javascript it will be useful. But take a look here: http://s-macke.github.io/jor1k/compile.html http://s-macke.github.io/jor1k/compile.html So you can use it in a C programming course for SMP systems. OpenMP is supported for example.
benjamincburns 12y ago
I think it was over a year ago that I hacked together the network support for this, submitted a few links to HN, Slashdot, and Reddit, and then proceeded to neglect it more or less entirely. It's really cool to wake up one day and see not only that it all still works, but that it's thriving, with heaps of new features. This is some killer work, Sebastian! Please do get in touch with me if the router goes down. I can't believe it's stayed up this whole time! Edit: Please do read the README.md on GitHub, but demo links are here: Demo (1 core): http://s-macke.github.com/jor1k/ http://s-macke.github.com/jor1k/ Demo (2 cores): http://s-macke.github.io/jor1k/index.html?cpu=smp&n=2 http://s-macke.github.io/jor1k/index.html?cpu=smp&n=2 And increase the "n" querystring argument for number of cores up to 16.
otoburb 12y ago
OpenRISC 2000 may end up converging on the RISC-V ISA. A blog post and accompanying comment[1] shed a bit of light on David Patterson (creator of the original RISC instruction set[2]) and his team's decision to setup an entirely new project. EDIT: Looks like the RISC-V FAQ references the same blog post since so many people ask the same question.[3] [1] https://blog.riscv.org/2014/10/why-not-build-on-openrisc/ https://blog.riscv.org/2014/10/why-not-build-on-openrisc/ [2] http://en.wikipedia.org/wiki/David_Patterson_(computer_scientist) http://en.wikipedia.org/wiki/David_Patterson_(computer_scien... [3] http://riscv.org/faq.html#otherisas http://riscv.org/faq.html#otherisas
- s-macke 12y ago
  I am still fascinated by the sheer number of RISC CPUs out there. But more amazing than this is their similarity. I think we should develop a new (abstract) RISC CPU which combines all in one architecture :-) . Joking apart, as a developer of jor1k I am also interested in RISC-V and constantly follow their progress. I am still not sure, if RISC-V is just OpenRISC 2.0 or a competitor. The technical keypoints of criticism of the OpenRISC architecture are true, but show me an architecture, which is free of bad design decisions? The problem is usually not to build a new instruction set. It is in fact the easiest part I would say. The most time consuming part is to build the toolchain including, emulators, Linux, gcc, binutils, libc and tons of architecture dependent libraries and programs (gdb, strace, ltrace, libffi, xpcom, ...) . And here RISC-V begins again from scratch which is a little bit sad. You forgot to tell, that the RISC-V team build their own Javascript based emulator at https://github.com/ucb-bar/riscv-angel https://github.com/ucb-bar/riscv-angel
  - otoburb 12y ago
    I didn't even realize they had built their own JS emulator. I'm not sure why they didn't choose to adopt much of the OpenRISC work - was hoping that their FAQ would have had more details, but it only referenced the blog post. However, it seems they're rather committed and have funding, so hopefully they can carry on the open and free RISC torch, whether alongside or via convergence with OpenRISC.
  - 12y ago

43 points by s-macke 12y ago

Just some technical details: The cores are emulated in one worker thread because shared memory in threads is still not supported by the engines. You can use "htop" to see the cores at work. You can run a multithreaded fractal generator with "mandelpar" too.

benjamincburns 12y ago
Is there any performance improvement on multithreaded tasks with SMP enabled?
- s-macke 12y ago
  Not yet. But when shared memory arrays become available in Javascript it will be useful. But take a look here: http://s-macke.github.io/jor1k/compile.html http://s-macke.github.io/jor1k/compile.html So you can use it in a C programming course for SMP systems. OpenMP is supported for example.

benjamincburns 12y ago

I think it was over a year ago that I hacked together the network support for this, submitted a few links to HN, Slashdot, and Reddit, and then proceeded to neglect it more or less entirely. It's really cool to wake up one day and see not only that it all still works, but that it's thriving, with heaps of new features. This is some killer work, Sebastian! Please do get in touch with me if the router goes down. I can't believe it's stayed up this whole time! Edit: Please do read the README.md on GitHub, but demo links are here: Demo (1 core): http://s-macke.github.com/jor1k/ http://s-macke.github.com/jor1k/ Demo (2 cores): http://s-macke.github.io/jor1k/index.html?cpu=smp&n=2 http://s-macke.github.io/jor1k/index.html?cpu=smp&n=2 And increase the "n" querystring argument for number of cores up to 16.

otoburb 12y ago

OpenRISC 2000 may end up converging on the RISC-V ISA. A blog post and accompanying comment[1] shed a bit of light on David Patterson (creator of the original RISC instruction set[2]) and his team's decision to setup an entirely new project. EDIT: Looks like the RISC-V FAQ references the same blog post since so many people ask the same question.[3] [1] https://blog.riscv.org/2014/10/why-not-build-on-openrisc/ https://blog.riscv.org/2014/10/why-not-build-on-openrisc/ [2] http://en.wikipedia.org/wiki/David_Patterson_(computer_scientist) http://en.wikipedia.org/wiki/David_Patterson_(computer_scien... [3] http://riscv.org/faq.html#otherisas http://riscv.org/faq.html#otherisas

s-macke 12y ago
I am still fascinated by the sheer number of RISC CPUs out there. But more amazing than this is their similarity. I think we should develop a new (abstract) RISC CPU which combines all in one architecture :-) . Joking apart, as a developer of jor1k I am also interested in RISC-V and constantly follow their progress. I am still not sure, if RISC-V is just OpenRISC 2.0 or a competitor. The technical keypoints of criticism of the OpenRISC architecture are true, but show me an architecture, which is free of bad design decisions? The problem is usually not to build a new instruction set. It is in fact the easiest part I would say. The most time consuming part is to build the toolchain including, emulators, Linux, gcc, binutils, libc and tons of architecture dependent libraries and programs (gdb, strace, ltrace, libffi, xpcom, ...) . And here RISC-V begins again from scratch which is a little bit sad. You forgot to tell, that the RISC-V team build their own Javascript based emulator at https://github.com/ucb-bar/riscv-angel https://github.com/ucb-bar/riscv-angel
- otoburb 12y ago
  I didn't even realize they had built their own JS emulator. I'm not sure why they didn't choose to adopt much of the OpenRISC work - was hoping that their FAQ would have had more details, but it only referenced the blog post. However, it seems they're rather committed and have funding, so hopefully they can carry on the open and free RISC torch, whether alongside or via convergence with OpenRISC.
- 12y ago