4 ms·

Cost. More cache means bigger die size and lower yield. Also once the area of the cache gets too big, the latency increases too much. That's why the P3 moved th

• sliverstorm 12y ago
  Also density. DRAM is orders of magnitude more dense per silicon area than SRAM, but you can't generally put DRAM cells on the same chip as the CPU.
• Sharlin 12y ago
  Yes. It's important to realize that at current clock speeds, much of the latency is simply the direct result of the finite speed of light. You simply can't fit gigabytes of memory in a location that's physically close enough to the processor.
  • techrat 12y ago
    Hence the location of memory slots always being physically parallel to the CPU socket, squiggles in the traces in the innermost lines from memory socket to CPU (to equal the distance of the longer traces along the edges of the socket to the CPU so timings remain in sync), and why die shrinks are more important for performance than scaling out... If a chip is too physically big, the speed of light can limit its performance before other inefficiencies will. Really fascinating and reinforces how no matter how one can imagine how much "faster" computers will get in the future, there is still that speed limit of information.
  • xxs 12y ago
    >>much of the latency is simply the direct result of the finite speed of light.<< This should be in bold: besides the 6 transistors per bit for L1, there is so much space to fit on a die that's close enough to the core.