uop fusion is described in Agner's microarchitecture [1] and also on Intel's optimization manual [2, §2.3.2.6]. I don't know of any breakdown of uops for AMD's

uop fusion is described in Agner's microarchitecture [1] and also on Intel's optimization manual [2, §2.3.2.6]. I don't know of any breakdown of uops for AMD's chips, but it's reasonable to assume that `add reg, mem` does that; it's the `add mem, reg` case which forces at least 2 fused uops to be issued. EDIT: OK, apparently an AMD "macro-op" can actually be a 3-uop read-modify-write operation [3]. This is news to me. [1] http://agner.org/optimize/microarchitecture.pdf http://agner.org/optimize/microarchitecture.pdf [2] http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html http://www.intel.com/content/www/us/en/architecture-and-tech... [3] http://www.realworldtech.com/bulldozer/5/ http://www.realworldtech.com/bulldozer/5/