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> For instance they claim an ADD mem, reg instruction would be translated into three 3 uops. This is definitely not the case, x86 chips can do a load+arith_op o
by pbsd 12y ago
> For instance they claim an ADD mem, reg instruction would be translated into three 3 uops. This is definitely not the case, x86 chips can do a load+arith_op or a store+arith_op in the same uop.
Sort of. An `add mem, reg` operation will result in 3 uops, but 2 of them will be fused (treated as a single one) throughout the pipeline until they're dispatched to execution units. This was introduced in the Pentium M, and perfected in Core 2---both of which released much later than the linked paper.
- wsxcde 12y agoWhat's the source for this? I've definitely worked on an AMD processor which executed add reg, mem as a single uop. I can't comment on Intel's uop fusion and uop cracking shenanigans because I don't understand them very well.
- pbsd 12y agouop fusion is described in Agner's microarchitecture [1] and also on Intel's optimization manual [2, §2.3.2.6]. I don't know of any breakdown of uops for AMD's chips, but it's reasonable to assume that `add reg, mem` does that; it's the `add mem, reg` case which forces at least 2 fused uops to be issued. EDIT: OK, apparently an AMD "macro-op" can actually be a 3-uop read-modify-write operation [3]. This is news to me. [1] http://agner.org/optimize/microarchitecture.pdf http://agner.org/optimize/microarchitecture.pdf [2] http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html http://www.intel.com/content/www/us/en/architecture-and-tech... [3] http://www.realworldtech.com/bulldozer/5/ http://www.realworldtech.com/bulldozer/5/
- brigade 12y agoSince K7/K8 at least. See Agner Fog's microarchitecture manuals, or Anandtech's core/K8 comparison. You're probably thinking in terms of AMD's "macro-ops" which is basically the same thing as Intel's fused uops.