3 ms·
One reason would be that power uses 8 way smt while Intel (with hyper threading) uses 2 way smt. If your code has tons of cache misses you will gain greatly fro
by en4bz 12y ago
One reason would be that power uses 8 way smt while Intel (with hyper threading) uses 2 way smt. If your code has tons of cache misses you will gain greatly from 8way smt since another thread can run on the physical core while other threads are waiting for memory. I suspect PPC would do very poorly with High performance code with low cache misses. However for something like a Java program where cache misses are abundant I would expect to see a big boost in performance. The benchmarks above are therefore completely dependant on the cache size.
- CountHackulus 12y agoI worked with the people at IBM who did optimization work for Java on Power. The ridiculous amount of work they did was amazing. There's dozens upon dozens of compiler papers and presentations that are more or less power specific. It was an exciting, and stressful, thing to be a part of.
- PhuFighter 12y agoI think if you look closely at the specs, I think the Xeon has about 2.5MB of L3 per core, while P8 has about 8MB of L3/core. There are bigger differences than this. But the examples above have both processors set at SMT2 (~30 seconds vs ~10 seconds). Differences are greater for SMT4 and SMT8. Of course, if your code fits nicely into the L3 - e.g. if your hot code consumes 3MB, then Power8 will be a bigger winner since there may be more thrashing for the x86 chip - unless, of course, the prediction routines is straight forward and the cacheline can be prefetched (think sequential access vs random access). From what I saw elsewhere, highly parallel code runs faster on P8, where as single thread perf is faster on x86. So if your HPC app is basically single threaded on one of your compute nodes, then that would be faster. But if your HPC code is highly multithreaded on the core, then P8 may surprise you.