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I'll rant for a moment here, because I think this is something that the Simple CPU link has the potential to get right, and that I think is a common pitfall wit

by jwise0 12y ago

I'll rant for a moment here, because I think this is something that the Simple CPU link has the potential to get right, and that I think is a common pitfall with digital design tutorials. I think one of the pain points that you commonly see with tutorials is the concept that the hard part is the language. As a digital designer, I think that's explicitly not the case: just like teaching functional programming, the syntax is not the challenge, but the mode of thinking. Digital design is a skill that really requires deep thought about what a given piece of syntax will compile down to; it's possible to skim over the "building blocks" of software (for instance, it is possible to be a very good JavaScript programmer without knowing what the JIT will transform your code to), but in order to build effective (or even possible-to-synthesize!) hardware designs, I believe that it is very important to start with the fundamentals of how hardware actually works. So, I plead: if you have cause to write a digital design book, don't write it as a "Verilog for Computer Scientists"! Verilog is a big language, and not all of it is good for writing hardware. What you really want is "Digital Design for Computer Scientists".

sliverstorm 12y ago
Yes, the two key hurdles to HDL are (in my opinion): - Being able to think parallel. Software is sequential by default, HDL is parallel by default. - Understanding what you want to build. If you can't draw what you want, you probably can't write good HDL. There's a reason it's called Hardware Description Language, and not "JS2GATES". In a sense, HDL is really just text-based schematics. Case in point: http://www.allaboutcircuits.com/vol_5/chpt_7/8.html http://www.allaboutcircuits.com/vol_5/chpt_7/8.html When you think "HDL" you probably think of Verilog or VHDL, but SPICE netlists is also an HDL.
- DubiousPusher 12y ago
  >Being able to think parallel. Software is sequential by default, HDL is parallel by default. Totally. When working through the nand2tetris stuff, several of my designs fell on their face because I started thinking of multistep circuit logic as sequential, forgetting that junk results aren't discarded by the "flow" but that their values are always "evaluated" and fed into downstream logic.

by jwise0 12y ago

sliverstorm 12y ago

Yes, the two key hurdles to HDL are (in my opinion): - Being able to think parallel. Software is sequential by default, HDL is parallel by default. - Understanding what you want to build. If you can't draw what you want, you probably can't write good HDL. There's a reason it's called Hardware Description Language, and not "JS2GATES". In a sense, HDL is really just text-based schematics. Case in point: http://www.allaboutcircuits.com/vol_5/chpt_7/8.html http://www.allaboutcircuits.com/vol_5/chpt_7/8.html When you think "HDL" you probably think of Verilog or VHDL, but SPICE netlists is also an HDL.

DubiousPusher 12y ago
>Being able to think parallel. Software is sequential by default, HDL is parallel by default. Totally. When working through the nand2tetris stuff, several of my designs fell on their face because I started thinking of multistep circuit logic as sequential, forgetting that junk results aren't discarded by the "flow" but that their values are always "evaluated" and fed into downstream logic.