3 ms·

Ah, can this be done effectively in old old processes? I guess I figured to beat an FPGA (many of which run in the latest-and-greatest process) you'd want a new

• aidenn0 12y ago
  FPGAs are very slow and power hungry compared to ASICs at the same node, so an older process could be effective.
  • thesz 12y ago
    Not quite slow, actually. And not power hungry. Altera top FPGAs have ~20W footprint with FLOPS performance about same as Intel Core i7 CPUs. I estimated that it might be energy-wise better to go to FPGA for at least some HPC workloads. Also, the speed difference between ASIC and FPGA designs are not in an order of magnitude. E.g., you'll have hard time optimizing your design for 2GHz and may even go to physical design for some components, while having 250MHz FPGA design is not a hard thing. I estimated that right now difference is two-to-four fold - 500MHz in ASIC, 100-200MHz in FPGA, with same development effort (Verilog/VHDL, no library specialization). Going physical in ASIC design means you'll stretch your development time by months or even years. Also you'll have to drop out some nice millions of dollars for CAD software licenses.
    • legulere 12y ago
      That's because you're just using the floating point unit within the FPGA. If you have general logic it will be slower and less power-efficient by several factors compared to an ASIC.