3 ms·

Out of curiosity, what process do you have in mind? At $250k/metal layer, most modern processes (with eight to twelve metal layers and many base layers) are goi

Out of curiosity, what process do you have in mind? At $250k/metal layer, most modern processes (with eight to twelve metal layers and many base layers) are going to run you closer to $5M just for the masks. Or are you saying there are places that will do a modern metal mask set as cheap as $250k?

wmf 12y ago
AFAIK masks for old processes are cheap. I don't think the Avalon Bitcoin ASIC guy spent $1M for his 130 nm NRE. There are also shared mask services like MOSIS.
- sliverstorm 12y ago
  Ah, can this be done effectively in old old processes? I guess I figured to beat an FPGA (many of which run in the latest-and-greatest process) you'd want a newer process.
  - aidenn0 12y ago
    FPGAs are very slow and power hungry compared to ASICs at the same node, so an older process could be effective.
    - thesz 12y ago
      Not quite slow, actually. And not power hungry. Altera top FPGAs have ~20W footprint with FLOPS performance about same as Intel Core i7 CPUs. I estimated that it might be energy-wise better to go to FPGA for at least some HPC workloads. Also, the speed difference between ASIC and FPGA designs are not in an order of magnitude. E.g., you'll have hard time optimizing your design for 2GHz and may even go to physical design for some components, while having 250MHz FPGA design is not a hard thing. I estimated that right now difference is two-to-four fold - 500MHz in ASIC, 100-200MHz in FPGA, with same development effort (Verilog/VHDL, no library specialization). Going physical in ASIC design means you'll stretch your development time by months or even years. Also you'll have to drop out some nice millions of dollars for CAD software licenses.
      - legulere 12y ago
        That's because you're just using the floating point unit within the FPGA. If you have general logic it will be slower and less power-efficient by several factors compared to an ASIC.
ChuckMcM 12y ago
At the time (and this was 2000, not today) TSMC had a 'boiler plate' for most FPGA families, which was the silicon and metal layers were already done, and all you needed to supply was the interconnection layer (which was generally all metal). The advantage was the single mask versus a full set. The downside was that it wasn't as compact as it could be, but this was essentially 'fpga -> asic' minimum cost, and at the time the FPGAs themselves were quite expensive chips. So if you had designed something you could do this to convert to an ASIC and then pop out a more cost effective version. That changed with the 90 nm node I believe (Xilinx had a bunch of 'Kiss your ASIC goodbye' type advertising at the time) where they had gotten the cost of the FPGA down below even this sort of inexpensive ASIC. If you are all in, you just hand over your HDL code and test vectors and they crank it through on your process of choice, and poof out comes chips. At which point you are exactly a fabless semiconductor company :-).

wmf 12y ago

AFAIK masks for old processes are cheap. I don't think the Avalon Bitcoin ASIC guy spent $1M for his 130 nm NRE. There are also shared mask services like MOSIS.

sliverstorm 12y ago
Ah, can this be done effectively in old old processes? I guess I figured to beat an FPGA (many of which run in the latest-and-greatest process) you'd want a newer process.
- aidenn0 12y ago
  FPGAs are very slow and power hungry compared to ASICs at the same node, so an older process could be effective.
  - thesz 12y ago
    Not quite slow, actually. And not power hungry. Altera top FPGAs have ~20W footprint with FLOPS performance about same as Intel Core i7 CPUs. I estimated that it might be energy-wise better to go to FPGA for at least some HPC workloads. Also, the speed difference between ASIC and FPGA designs are not in an order of magnitude. E.g., you'll have hard time optimizing your design for 2GHz and may even go to physical design for some components, while having 250MHz FPGA design is not a hard thing. I estimated that right now difference is two-to-four fold - 500MHz in ASIC, 100-200MHz in FPGA, with same development effort (Verilog/VHDL, no library specialization). Going physical in ASIC design means you'll stretch your development time by months or even years. Also you'll have to drop out some nice millions of dollars for CAD software licenses.
    - legulere 12y ago
      That's because you're just using the floating point unit within the FPGA. If you have general logic it will be slower and less power-efficient by several factors compared to an ASIC.

ChuckMcM 12y ago

At the time (and this was 2000, not today) TSMC had a 'boiler plate' for most FPGA families, which was the silicon and metal layers were already done, and all you needed to supply was the interconnection layer (which was generally all metal). The advantage was the single mask versus a full set. The downside was that it wasn't as compact as it could be, but this was essentially 'fpga -> asic' minimum cost, and at the time the FPGAs themselves were quite expensive chips. So if you had designed something you could do this to convert to an ASIC and then pop out a more cost effective version. That changed with the 90 nm node I believe (Xilinx had a bunch of 'Kiss your ASIC goodbye' type advertising at the time) where they had gotten the cost of the FPGA down below even this sort of inexpensive ASIC. If you are all in, you just hand over your HDL code and test vectors and they crank it through on your process of choice, and poof out comes chips. At which point you are exactly a fabless semiconductor company :-).