3 ms·

I love stuff like this. One thing I've wanted for awhile, but not been able to find is off the shelf ASIC making. For instance, you could take a design like t

by MCRed 12y ago

I love stuff like this. One thing I've wanted for awhile, but not been able to find is off the shelf ASIC making. For instance, you could take a design like this, or something built for FPGAs, and then turn that into a contract manufacturer who would produce screens and then custom ASICs in low volume. You can do this with PCBs and just about every other part of the hardware stack, but not ASICs. Part of the reason, of course, is that laying out an ASIC is a time consuming and expensive proposition-- but I wonder if there isn't a huge opportunity to write software to take a FPGA configuration and algorithmically turn it into the screens to do lithography, which could then be sent to a fab. Of course you'd have to require specific processes and pre-defined submodules that represent the various gates. Back when there was no ASICs for the scrypt hash I wanted to make one. Anyway, I think there might be a huge opportunity there for someone with the skills.

sliverstorm 12y ago
What do you see this actually achieving? You make an ASIC for very specific reasons; FPGAs already do a great job of bridging the gap, including in production. For example many budget oscilloscopes these days run with a microprocessor-FPGA pair. As for an scrypt ASIC, I don't believe you could just whip one up over a weekend. I don't know how the scrypt ASIC nut was eventually cracked, but the algorithm was specifically chosen to be hard to make an ASIC for. It requires fast memory and lots of it. If you make yourself a massively parallel ASIC and bolt it onto some GDDR5... that starts to look a lot like a GPU.
- wmf 12y ago
  scrypt was intended to be memory-hard but it failed somewhat. There is a time-memory trade off that significantly reduces the amount of memory needed. Then the altcoin people also used scrypt wrong, setting a memory size of 128 KB which is trivial to include in an ASIC.
ChuckMcM 12y ago
Actually these days folks like TSMC will take your Xilinx or Altera program file and run it through their converter to make you a copy of that chip as an ASIC. The challenge is that a metal layer mask for a 300mm wafer (which is pretty much what you need since the FPGA substrate is pretty standard) will set you back about a quarter million dollars. And unfortunately you can't have them make just 1 wafer with it, a cassette holds a minimum number of wafers (last time I was thinking about this it was 6 wafers but that may have changed) and of course you have to schedule them on a line (sometimes called a 'wafer start') and then they will go through an pop out the other side and now you have to dice them up and package them. So you end up with probably 10,000 examples of your ASIC which you've paid about a million and a half for. One of the amazing changes has been that your FPGA can cost less than your ASIC in small (< 10K) quantities.
- sliverstorm 12y ago
  Out of curiosity, what process do you have in mind? At $250k/metal layer, most modern processes (with eight to twelve metal layers and many base layers) are going to run you closer to $5M just for the masks. Or are you saying there are places that will do a modern metal mask set as cheap as $250k?
  - wmf 12y ago
    AFAIK masks for old processes are cheap. I don't think the Avalon Bitcoin ASIC guy spent $1M for his 130 nm NRE. There are also shared mask services like MOSIS.
    - sliverstorm 12y ago
      Ah, can this be done effectively in old old processes? I guess I figured to beat an FPGA (many of which run in the latest-and-greatest process) you'd want a newer process.
      - aidenn0 12y ago
        FPGAs are very slow and power hungry compared to ASICs at the same node, so an older process could be effective.
        thesz 12y ago
        Not quite slow, actually. And not power hungry. Altera top FPGAs have ~20W footprint with FLOPS performance about same as Intel Core i7 CPUs. I estimated that it might be energy-wise better to go to FPGA for at least some HPC workloads. Also, the speed difference between ASIC and FPGA designs are not in an order of magnitude. E.g., you'll have hard time optimizing your design for 2GHz and may even go to physical design for some components, while having 250MHz FPGA design is not a hard thing. I estimated that right now difference is two-to-four fold - 500MHz in ASIC, 100-200MHz in FPGA, with same development effort (Verilog/VHDL, no library specialization). Going physical in ASIC design means you'll stretch your development time by months or even years. Also you'll have to drop out some nice millions of dollars for CAD software licenses.
jjoonathan 12y ago
Altera used to do this a few years ago (the trademark was "HardCopy," I believe). If anyone knows why they stopped, I'd love to hear. My guess is that the HardCopy ASICs significantly underperformed "manually designed" ASICs while costing almost as much: they couldn't take advantage of ASIC-specific strategies, but they still had all the fixed costs associated with a die run.
teraflop 12y ago
MOSIS (https://www.mosis.com/ https://www.mosis.com/) will do runs of 20-100 ASICs. I've never used them but I just requested a couple of quotes, and it looks like their prices range from a few thousand dollars to a few tens of thousands, depending on process and size.
- chrisBob 12y ago
  In the MEMS world we have something similar to this where you don't get a full wafer you just pay for copies of the device you design to be put on the next run. In this case it makes even more sense because the processes are much more standardized for IC work.
- robomartin 12y ago
  I used MOSIS years ago for custom image sensors. Amazing resource. I can't say much more than I think each spin was about $150K.
- deleted 12y ago
  [deleted]
coupdejarnac 12y ago
I'm curious what the breakeven point is for a small ASIC production run vs using FPGAs. It seems FPGAs are so cheap these days, you'd have to do a production of several 10s of thousands of ASICs to make it worthwhile.
- fnordfnordfnord 12y ago
  Or have another good reason, like needing it to go fast.
wmf 12y ago
There are plenty of companies that do FPGA-to-ASIC conversion. Gate arrays can also be an intermediate step that only require a small number of mask layers instead of a full set. This diagram is interesting: http://www.easic.com/products/easicopy-cell-based-asic-migration-path/ http://www.easic.com/products/easicopy-cell-based-asic-migra...

by MCRed 12y ago

sliverstorm 12y ago

What do you see this actually achieving? You make an ASIC for very specific reasons; FPGAs already do a great job of bridging the gap, including in production. For example many budget oscilloscopes these days run with a microprocessor-FPGA pair. As for an scrypt ASIC, I don't believe you could just whip one up over a weekend. I don't know how the scrypt ASIC nut was eventually cracked, but the algorithm was specifically chosen to be hard to make an ASIC for. It requires fast memory and lots of it. If you make yourself a massively parallel ASIC and bolt it onto some GDDR5... that starts to look a lot like a GPU.

wmf 12y ago
scrypt was intended to be memory-hard but it failed somewhat. There is a time-memory trade off that significantly reduces the amount of memory needed. Then the altcoin people also used scrypt wrong, setting a memory size of 128 KB which is trivial to include in an ASIC.

ChuckMcM 12y ago

Actually these days folks like TSMC will take your Xilinx or Altera program file and run it through their converter to make you a copy of that chip as an ASIC. The challenge is that a metal layer mask for a 300mm wafer (which is pretty much what you need since the FPGA substrate is pretty standard) will set you back about a quarter million dollars. And unfortunately you can't have them make just 1 wafer with it, a cassette holds a minimum number of wafers (last time I was thinking about this it was 6 wafers but that may have changed) and of course you have to schedule them on a line (sometimes called a 'wafer start') and then they will go through an pop out the other side and now you have to dice them up and package them. So you end up with probably 10,000 examples of your ASIC which you've paid about a million and a half for. One of the amazing changes has been that your FPGA can cost less than your ASIC in small (< 10K) quantities.

sliverstorm 12y ago
Out of curiosity, what process do you have in mind? At $250k/metal layer, most modern processes (with eight to twelve metal layers and many base layers) are going to run you closer to $5M just for the masks. Or are you saying there are places that will do a modern metal mask set as cheap as $250k?
- wmf 12y ago
  AFAIK masks for old processes are cheap. I don't think the Avalon Bitcoin ASIC guy spent $1M for his 130 nm NRE. There are also shared mask services like MOSIS.
  - sliverstorm 12y ago
    Ah, can this be done effectively in old old processes? I guess I figured to beat an FPGA (many of which run in the latest-and-greatest process) you'd want a newer process.
    - aidenn0 12y ago
      FPGAs are very slow and power hungry compared to ASICs at the same node, so an older process could be effective.
      - thesz 12y ago
        Not quite slow, actually. And not power hungry. Altera top FPGAs have ~20W footprint with FLOPS performance about same as Intel Core i7 CPUs. I estimated that it might be energy-wise better to go to FPGA for at least some HPC workloads. Also, the speed difference between ASIC and FPGA designs are not in an order of magnitude. E.g., you'll have hard time optimizing your design for 2GHz and may even go to physical design for some components, while having 250MHz FPGA design is not a hard thing. I estimated that right now difference is two-to-four fold - 500MHz in ASIC, 100-200MHz in FPGA, with same development effort (Verilog/VHDL, no library specialization). Going physical in ASIC design means you'll stretch your development time by months or even years. Also you'll have to drop out some nice millions of dollars for CAD software licenses.

jjoonathan 12y ago

Altera used to do this a few years ago (the trademark was "HardCopy," I believe). If anyone knows why they stopped, I'd love to hear. My guess is that the HardCopy ASICs significantly underperformed "manually designed" ASICs while costing almost as much: they couldn't take advantage of ASIC-specific strategies, but they still had all the fixed costs associated with a die run.

teraflop 12y ago

MOSIS (https://www.mosis.com/ https://www.mosis.com/) will do runs of 20-100 ASICs. I've never used them but I just requested a couple of quotes, and it looks like their prices range from a few thousand dollars to a few tens of thousands, depending on process and size.

chrisBob 12y ago
In the MEMS world we have something similar to this where you don't get a full wafer you just pay for copies of the device you design to be put on the next run. In this case it makes even more sense because the processes are much more standardized for IC work.
robomartin 12y ago
I used MOSIS years ago for custom image sensors. Amazing resource. I can't say much more than I think each spin was about $150K.
deleted 12y ago
[deleted]

coupdejarnac 12y ago

I'm curious what the breakeven point is for a small ASIC production run vs using FPGAs. It seems FPGAs are so cheap these days, you'd have to do a production of several 10s of thousands of ASICs to make it worthwhile.

fnordfnordfnord 12y ago
Or have another good reason, like needing it to go fast.

wmf 12y ago

There are plenty of companies that do FPGA-to-ASIC conversion. Gate arrays can also be an intermediate step that only require a small number of mask layers instead of a full set. This diagram is interesting: http://www.easic.com/products/easicopy-cell-based-asic-migration-path/ http://www.easic.com/products/easicopy-cell-based-asic-migra...