The problem is that they add a new language feature for every new use case instead of trying to make features fit together in a nice compact core & building on

The problem is that they add a new language feature for every new use case instead of trying to make features fit together in a nice compact core & building on top of that core (in other words 'modern language design'). Systemverilog now has ~250 keywords, do you think you know all of them? There are so many that they allow you to selectively disable keywords using compiler pragmas. In python there are only 33 keywords! VHDL avoided this issue because they mostly copied the ADA language which was developed by competent language designers. I don't doubt the usefulness of a subset of systemverilog, but as a language it's very badly designed.