Its a nice simple design. Interesting to see it python instead of the usual verilog/vhdl Real uarts tend to implement FIFOs and oversample and do control sign

Its a nice simple design. Interesting to see it python instead of the usual verilog/vhdl Real uarts tend to implement FIFOs and oversample and do control signals. The virtual 16550 linked below oversamples at 16x and the generic verilog uart below does at least try to sniff at the center of the bit clock even if I don't think it oversamples. Here's a generic verilog uart http://opencores.org/project,osdvu http://opencores.org/project,osdvu here's a virtual 16550 http://opencores.org/project,uart16550 http://opencores.org/project,uart16550 Those projects would be logical paths of inspiration to extend the python uart. You could probably just steal/borrow the PDF spec sheet for the virtual 16550 and use that as a spec to implement the python uart.