4 ms·

That's what I thought, too, but I asked an electrical engineer friend of mine, and he said they would increase power. I just looked it up now, using the term "d

That's what I thought, too, but I asked an electrical engineer friend of mine, and he said they would increase power. I just looked it up now, using the term "die shrink" (couldn't think of it earlier), and, sure enough, you're right. Not sure why he said otherwise...

daeken 12y ago
All else being equal, it drops consumption. But generally when you go down in process, you increase what you pack on the die, bringing the power back up.
- masklinn 12y ago
  The A7 doesn't really do that though, it was created in no small part to provide the same power as the A8 with much better efficiency, and to be paired with an A15 in big.LITTLE for transient high load (which isn't necessary in a smartwatch)
- akgerber 12y ago
  Phone-oriented SoCs have aggressive frequency scaling and power gating, such that the newer chipsets have lower power consumption in ordinary usage and only scale up to similar power usage in high-utilization applications.
lpmay 12y ago
Depending on the context, your friend may be right. Power dissipation in a CMOS gate is made up of two primary components: static leakage and dynamic losses. Dynamic losses are related to the "dissipation" capacitance (Cdiss or Cpd in CMOS datasheets) and the switching frequency. If you want to understand why, consider charging an RC circuit. How much energy is lost to the resistor and how much is stored in the capacitor at the end of charging? How does the selection of the resistor and capacitor value impact this ratio? So for minimum dynamic loss you want to minimize Cdiss which involves making gates as small as possible. However, this makes the static leakage higher. So it may not be universally as simple as "a smaller process is lower power". For a system which spends most of it's time in sleep, or clocks slowly it may actually be better to eat the dynamic loss of a larger process in order to get the lower leakage, which is something I believe TI did with some of the FRAM '430 parts (but I can't find the link now).

daeken 12y ago

All else being equal, it drops consumption. But generally when you go down in process, you increase what you pack on the die, bringing the power back up.

masklinn 12y ago
The A7 doesn't really do that though, it was created in no small part to provide the same power as the A8 with much better efficiency, and to be paired with an A15 in big.LITTLE for transient high load (which isn't necessary in a smartwatch)
akgerber 12y ago
Phone-oriented SoCs have aggressive frequency scaling and power gating, such that the newer chipsets have lower power consumption in ordinary usage and only scale up to similar power usage in high-utilization applications.

lpmay 12y ago

Depending on the context, your friend may be right. Power dissipation in a CMOS gate is made up of two primary components: static leakage and dynamic losses. Dynamic losses are related to the "dissipation" capacitance (Cdiss or Cpd in CMOS datasheets) and the switching frequency. If you want to understand why, consider charging an RC circuit. How much energy is lost to the resistor and how much is stored in the capacitor at the end of charging? How does the selection of the resistor and capacitor value impact this ratio? So for minimum dynamic loss you want to minimize Cdiss which involves making gates as small as possible. However, this makes the static leakage higher. So it may not be universally as simple as "a smaller process is lower power". For a system which spends most of it's time in sleep, or clocks slowly it may actually be better to eat the dynamic loss of a larger process in order to get the lower leakage, which is something I believe TI did with some of the FRAM '430 parts (but I can't find the link now).