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What's kind of neat is that you can put a downright silly amount of MIPS cores on something. Octeon, for example, with like 48 cores: http://www.cavium.com/OCT
by angersock 12y ago
What's kind of neat is that you can put a downright silly amount of MIPS cores on something. Octeon, for example, with like 48 cores:
http://www.cavium.com/OCTEON_MIPS64.html http://www.cavium.com/OCTEON_MIPS64.html
- wmf 12y agoThat's not specific to MIPS, though.
- shaurz 12y agoThe also have an ARM version: http://www.cavium.com/ThunderX_ARM_Processors.html http://www.cavium.com/ThunderX_ARM_Processors.html
- listic 12y agoWhy isn't anyone making servers with them?
- wmf 12y agoThunder isn't released yet. Cavium may also have trouble building a server ecosystem given their culture of total secrecy.
- justincormack 12y agoeg the quoted IO performance requiring a proprietary IP stack...
- Sanddancer 12y agoCavium's products have traditionally been geared more towards high end routers. Their chips have traditionally had massive amounts of networking bandwidth, but very little I/O for things like storage, or even RAM. Their ARM stuff looks like they may be about to change that, but details there are still rather scant.
- kps 12y agoXeon Phi currently ship with 57–61 cores (roughly P54C + AVX-512, IIRC). (Disclaimer: I once worked for Intel.) CPU cores are not a very big part of the die on most contemporary devices.
- valarauca1 12y agoQuestion (since you seem to know about the Phi) is the Phi x86_64 (and its extensions), or is it as black boxed every other GPU like device?
- Narishma 12y agoIt's basically a large number of in-order P5- (or Atom-) derived cores with 4-way SMT and beefed up SIMD capabilities (two 512-bit units per core).
- valarauca1 12y agoRISC chips have done this for a while. Oracle's T5 Niagara was something like 256 execution threads per socket. Power8 (also a RISC chip) supports 96 execution threads per socket. Most of a modern x86_64 chip is cache, and other System On Chip components (memory controller, PCIe controller, built in GPU), not necessarily what in the 80's and 90's we'd call the CPU.
- alexvoica 12y agoThe new coherency manager that we've designed allows us to build up to 64 clusters of 6 cores each.
- techdragon 12y agoI was looking for something like this recently, it's surprisingly hard to find with the internet flooded with SEO about ARM chips, it skews results and makes the other architectures harder to search for. I found more MIPS arch chips reading the open cores site than I ever did googling. Shame too, when there's fantastic hardware like this out there.