I personally think that a CPU with part / most of its instruction set microcode user-writable (read: push-inst / pop-inst) would be a potentially interesting in

I personally think that a CPU with part / most of its instruction set microcode user-writable (read: push-inst / pop-inst) would be a potentially interesting intermediate between FPGAs and CPUs. Because there isn't much conceptual difference between a CISC-that-is-a-RISC-internally (like, say, a modern x86 processor) and an FPGA beyond an FPGA having a more complete set of routing paths and a CPU not having the microcode user-writable. You could set up the current instructions to be optimized for the specific program you are running. Or even specific function, or lower. If you made it recursive you could potentially start running higher-level programming languages natively. And depending on how complex the microcode is, you could very well avoid the issues with "classic" high-level CPUs - namely that they sacrifice generality. They force you into the mindset of the specific high-level language if you want speed. It doesn't help with working memory bandwidth, but does help with instruction bandwidth, as it basically ends up compressing your machine code.