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Talking about the RISC-V Instruction Set Architecture http://riscv.org/ http://riscv.org/ Why would you need 128bit addressing? Isn't 64bit address space plen
by igravious 12y ago
Talking about the RISC-V Instruction Set Architecture
http://riscv.org/ http://riscv.org/
Why would you need 128bit addressing? Isn't 64bit address space plenty big? This isn't a "nobody'll need more than 640k scenario, right?"
https://gigaom2.files.wordpress.com/2014/08/requirements-table.gif https://gigaom2.files.wordpress.com/2014/08/requirements-tab...
- unwind 12y agoThere's motivation in the relevant part (RV128I Base Integer Instruction Set), starting on page 81 of the 2.0 ISA specification (https://s3-us-west-1.amazonaws.com/riscv.org/riscv-spec-v2.0.pdf https://s3-us-west-1.amazonaws.com/riscv.org/riscv-spec-v2.0...). A choice quote: It is not clear when a flat address space larger than 64 bits will be required. At the time of writing, the fastest supercomputer in the world as measured by the Top500 benchmark had over 1 PB of DRAM, and would require over 50 bits of address space if all the DRAM resided in a single address space. Some warehouse-scale computers already contain even larger quantities of DRAM, and new dense solid-state non-volatile memories and fast interconnect technologies might drive a demand for even larger memory spaces. Exascale systems research is targeting 100 PB memory systems, which occupy 57 bits of address space. At historic rates of growth, it is possible that greater than 64 bits of address space might be required before 2030.
- userbinator 12y agoif all the DRAM resided in a single address space Key point, and that's a huge "if". All large systems are NUMA, and trying to treat that like a uniform address space will be absolutely horrible because of the extreme latencies that arise.
- rch 12y agoYou're correct of course, but I wanted to point out that people shouldn't dismiss everything >64 bit out of hand based on this reasoning. There are architectures that can make use of those extra bits, and not just for addressing a universe of RAM. The Transmeta processors weren't perfect or anything, but there's merit in the VLIW approach. The first generation Crusoe chip was a 128 bit part, and the second was 256 bit; this was a decade ago, in chips designed for ultra-light consumer laptops. As I understand it, some key people from Transmeta ended up at P.A. Semi, which of course was acquired by Apple in 2008. I wouldn't be at all surprised if we're talking about VLIW architectures again by 2016 or at least 2020. - https://en.wikipedia.org/wiki/Transmeta_Efficeon https://en.wikipedia.org/wiki/Transmeta_Efficeon - https://en.wikipedia.org/wiki/Very_long_instruction_word https://en.wikipedia.org/wiki/Very_long_instruction_word
- aidenn0 12y agoI heard a rumor that the technical people from PASemi left after the acquisition. Does anyone have a reliable source to substantiate (or refute) that?
- aidenn0 12y ago1) Instruction size is irrelevant to address size 2) Yes Transmeta was VLIW internally, but I see that as an implementation-detail over other forms of superscalar; either way you have a linear stream of instructions generated by the compiler, with hardware turning that into parallel execution by the CPU at runtime. Calling that "VLIW" is about as interesting as calling a modern x86 "RISC."
- fulafel 12y agoMost numa machines are single address space, and it's a very handy thing to have. You can run general pupouse code on the machine for things that are not perf critical but need to get done.
- valarauca1 12y agoWith advent of memristor based memory it'll be possible today (at extremely high cost on the order of a medium nation's GDP) have on the orders of petabytes of what will functionally be RAM. Only ~6-7 tick/tock cycles are necessary for that to expand beyond the address space of 64bit addressing (~10^19).
- igravious 12y agoHow long is a tick/tock cycle? A few years? 3 * 7 = 21. So we'd need to prep for going beyond 64bit some time before 2035? Which chimes with the quote At historic rates of growth, it is possible that greater than 64 bits of address space might be required before 2030 that 'unwind' kindly gives in a sister comment. Seems like good forward planning but a little premature, no? These features must come at some cost. Surely you could have a re-vamp sometime around 2025?
- vidarh 12y agoWhy in the world would you plan a new architecture today, that will take years - easily a decade or more - to gain enough traction to be interesting, only to have to re-vamp it shortly afterwards? We have off the shelf x86 machines today that can fit enough memory to use about 43 bits to address it (at least in theory - depending on DIMM availability; 1TB/2TB is trivially available on the other hand). Now add in size of readily viable storage arrays or even network file systems and expect some people to want to be able to memory map "unreasonably" large files, and suddenly we're into 50+ bits today. It'd seem crazy to me if someone were to start planning a new processor architecture today without planning for addresses greater than 64 bits.
- JoeAltmaier 12y ago64 bits is a hell of a lot larger than 48 bits. You could make the argument that humanity will never need more than 64 bits, no matter how many trillions of years our race exists and uses computers.
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- sp332 12y agoIPv6-based addressing? :)
- chrisdew 12y agoClutching at straws here, but... One use case for 128 bit addressing is for a single-address-space OS running on a cluster. http://en.wikipedia.org/wiki/Single_address_space_operating_system http://en.wikipedia.org/wiki/Single_address_space_operating_... Pointers can have 32 bits for the IP address of the hosting node and 64 bits for the address within the node, and 32 bits spare for various flags.
- krylon 12y agoI have no idea if this is technically feasible, but it sounds like a sweet idea!