3 ms·
The arc processor line from Synopsys does this commercially, I believe. Risc-v seems to be trying to support this sort of thing; there is reserved opcode space
by rst 12y ago
The arc processor line from Synopsys does this commercially, I believe. Risc-v seems to be trying to support this sort of thing; there is reserved opcode space for implementation specific extensions
- TheLoneWolfling 12y agoI was under the impression that Synopsys' ARC processors were configurable at design time, not runtime. Or am I missing something? Have a link?