Okay. Your model looks like TTA - a machine that is built on bypasses. They are not new and they can be used to create very efficient chips (in terms of operat

Okay. Your model looks like TTA - a machine that is built on bypasses. They are not new and they can be used to create very efficient chips (in terms of operations/watt) for some fixed functions (precisely, FFT of 2^N). But they are 1) not fast in terms of raw performance for general purpose tasks, 2) not fast in terms of operating frequency and most important 3) prone to stall when present with non-deterministic delays like access to RAM. You can add whatever functional units you like to TTA design, including content-addressable memory in disguise as FIFO. TTA design with such device will be identical to what you've described above. I won't think you will improve performance very much with this trick. PS "not fast for general purpose tasks" - in some benchmarks TTA architectures executed gcc 10+ times slower than general purpose CPU with same frequency. "not fast in operating frequency" - TTA requires crossbar, which is slow in 2D. You cannot make it fast. "prone to stall" - you have to stop complete pipeline for a cache miss, otherwise you'll have divergence in execution.