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"The aging x86 architecture is beset by layers of architectural silt accreted from a succession of additions to the instruction set... Because of this excess ba
by fiatmoney 12y ago
"The aging x86 architecture is beset by layers of architectural silt accreted from a succession of additions to the instruction set... Because of this excess baggage, an x86 chip needs more transistors than its ARM-based equivalent"
I wish people would stop saying this. On the inside, x86 CPUs are basically RISC. There is a translation layer from the publicly facing instruction layer to the internal representation. The transistor and power budget for this translation layer is absolutely trivial.
Intel has an enormous amount of expertise in the actual manufacturing and design layers, as evidenced by the rate of improvement in their Atom CPUs (striking range of ARM, actually), integrated GPUs, and quasi-GPU compute cards. They are not in danger of "losing" in the long term in a performance or performance / watt race. The risk is they get disrupted due to all CPUs turning into a commodity in roughly the same way that RAM is a commodity.
- deleted 12y ago[deleted]
- the_mitsuhiko 12y agoWhat does the Mill have to do with either the article or the original comment? The Mill (while cool) is completely different and incomparable. What makes more sense is comparing an x64 to an ARM chip.
- tux1968 12y agoThe article, and quote from the root of this thread, may well be wrong in the detail but correct in the long-run as evidenced by the ideas exposed in the Mill. The comment I was responding too seemed to be generally discounting the possibility that there was any room to improve upon the internals of Intel CPU's which was the motivation for linking back to the Mill.
- jblow 12y agoYeah, as soon as the guy started saying this I discounted the whole article. Yes, maybe Apple will switch to A7 chips, but this author sure doesn't know enough about processors to have any kind of a privileged viewpoint. If one doesn't even know what uops are, and doesn't have a mental estimate of what percentage of i7 silicon is devoted to the instruction decoder, one doesn't get to write articles comparing Intel to ARM chips. Edit: Going back to the article I note the author is Jean-Louis Gassee, so this is just bizarre. He is kind of just talking out his ass and I would hope he'd know better than that, because whereas making stuff up is a survival skill in exec-land, being blatantly and demonstrably wrong about said make-ups is not.
- PhantomGremlin 12y ago> I note the author is Jean-Louis Gassee Yeah, not sure why anyone is interested in what Gassee has to say. He used to be "head of Apple's advanced product development", but was forced out for failing to deliver.[1] Also, he should get the small details right. He claims in the article The x86 nickname used to designate Wintel chips originates from the 8086 processor introduced in 1978 – itself a backward-compatible extension of the 8088…) This is exactly backwards. The 8086 was first, ahead of the 8088. Not sure why Gassee even felt he needed to throw that detail into the article (unless he's getting paid by the word), but if he's going to say it, he should at least check Wikipedia first.[2] [1] http://en.wikipedia.org/wiki/Jean-Louis_Gass%C3%A9e http://en.wikipedia.org/wiki/Jean-Louis_Gass%C3%A9e [2] http://en.wikipedia.org/wiki/Intel_8086 http://en.wikipedia.org/wiki/Intel_8086
- snowwrestler 12y agoGasse is probably better known to HN folks as the head of the BeOS system, which he did after Apple and was very well regarded in its day. In fact it was almost the next Mac OS, but he overpriced the deal. In addition he has been an excellent writer about technology businesses for years now.
- Symmetry 12y agoIt actually is true, though it's easy to exaggerate how important it is. Decoding an x86 instruction into the RISCish internal format isn't hard, but decoding 4 at once can be quite a challenge. There's no way to look at a single byte of the incoming instruction stream and figure out if it's the start of an instruction or not, you need to do a fair amount of decoding on each byte of the chunk that you fetch from I$ before you can tell where the instruction boundaries are. For A64 ARM you know that every fourth byte is going to be a new instruction start. I wouldn't put this penalty at more than maaaaybe 20% at the very most, but it is a thing. EDIT: And there are things like instruction gates that seriously are cruft that gums up how the memory system works, and some would argue that the x86 memory ordering constraints fall under this as well. On the other hand you should listen to Linus rant about how REP MOVS is the best thing since sliced bread that every other architecture is missing out on.
- ANTSANTS 12y agoOTOH you can cache the decoded microops (IIRC modern Intel chips do this, while modern AMD and the original Pentium cached instruction boundaries), and in thumb mode ARM is also variable length.
- higherpurpose 12y agoIntel chips even support 16-bit processing. How is that not baggage?
- ghaff 12y agoWe could also recycle lots of Intel's own verbiage from its own Itanium introduction :-) That didn't work out so well. There are some interesting questions related to whatever convergence of tablets and laptops ends up happening. But it's not clear to me that especially favors ARM. And, it's also a hybrid sort of device that seems so obvious yet Apple finally got tablets to take off by taking a different path. So I'm skeptical about time frames at a minimum.