That is more of an answer to routing and signal integrity problems of fast parallel interfaces, e.g. bandwidth. Most of the DRAM latency is inherent in the DRAM

That is more of an answer to routing and signal integrity problems of fast parallel interfaces, e.g. bandwidth. Most of the DRAM latency is inherent in the DRAM array itself (actually getting the data between dram array and sense amplifiers). Almost nobody cares about additional cycle of latency introduced by registered dimms, as it is essentially noise compared to precharge latency of the dram itself. This comes mostly from physical limits of what can be manufactured with reasonable power dissipation and reliability (see how "CAS Latency" grows at comparable rate to clock rate, ie. stays mostly comparable in wall-clock time)