3 ms·

It seems part of the answer to the latency question is to stack the ram on top of the dram controller, as mentioned in this recent article on Intel's Knights Co

• mud_dauber 12y ago
  Take a look at Micron's "HMC" stacked memory architecture. THIS is a move in the right direction. The short-term caveat is its focus on higher-performance niches like servers. It's a long time before you'll see this type of architecture in consumer PCs due to DDR3's dirt-cheap pricing.
• dfox 12y ago
  That is more of an answer to routing and signal integrity problems of fast parallel interfaces, e.g. bandwidth. Most of the DRAM latency is inherent in the DRAM array itself (actually getting the data between dram array and sense amplifiers). Almost nobody cares about additional cycle of latency introduced by registered dimms, as it is essentially noise compared to precharge latency of the dram itself. This comes mostly from physical limits of what can be manufactured with reasonable power dissipation and reliability (see how "CAS Latency" grows at comparable rate to clock rate, ie. stays mostly comparable in wall-clock time)