2 ms·
Apparently it's done through controlling the MTRR registers on the CPU: http://rere.qmqm.pl/~mirq/cache_as_ram_lb_09142006.pdf http://rere.qmqm.pl/~mirq/cache_
by simcop2387 12y ago
Apparently it's done through controlling the MTRR registers on the CPU:
http://rere.qmqm.pl/~mirq/cache_as_ram_lb_09142006.pdf http://rere.qmqm.pl/~mirq/cache_as_ram_lb_09142006.pdf