3 ms·

Cache Coherency Primer

alain94040 12y ago
Not very accurate with respect to recent cpus. But decent overview of cache coherency. EDIT: apologies for the harsh comment. I'm not aware of public information regarding recent cpus. I tried to give some more technical details in an answer below.
- bla2 12y ago
  What do recent cpus do differently?
  - alain94040 12y ago
    Just to pick a few statements: by default, loads can fetch stale data . No, not really. everything gets even more vague when Out of Order execution is involved . OOO is the new normal. Not to mention prefetching, which completely destroys any mental model of in-order memory access you could have. Architectures with a weak memory model do the minimum amount of work necessary in the core . I wish. weak memory is very complex. Look up synchronization barriers for an idea of how messy it gets. But again, for software developers, that article is good enough.
    - jblow 12y ago
      Sorry, but you are drastically underestimating the knowledge and experience of the author of the article for no other reason than to try and make yourself look smart, which is failing.
    - stinos 12y ago
      Maybe you are right, maybe you are wrong, but you'll have to come up with a proper and more in-depth explanation or article to convince anyone on HN from your standpoint. Now you are just laying down some buzzwords.
- forrestthewoods 12y ago
  You have successfully managed to reply to a detailed technical blog post in a manner that provides zero value to anyone and only serves to make you try to sound smarter than the original author. Good job. It'd be great if you could provide value by giving, or linking to, an explanation as to why the post is "not very accurate with respect to recent cpus".
willvarfar 12y ago
If you liked this excellent overview, and you're not too tired of me going on about the new Mill CPU architecture already, you may like that Mill loads specify their retire cycle and represent memory at retire time rather than issue time. The Mill is therefore immune to aliasing races. And this works between cores too!
- zxcdw 12y ago
  Thanks for your hard work on the Mill CPU. It is truly fascinating to learn about it! I've been waiting for the Pipeline talk for the past week, checking the website few times a day. :) And for those who are interested in this type of thing, here's a talk about the Mill CPU memory system which also touches caches: http://millcomputing.com/docs/memory/ http://millcomputing.com/docs/memory/

Not very accurate with respect to recent cpus. But decent overview of cache coherency. EDIT: apologies for the harsh comment. I'm not aware of public information regarding recent cpus. I tried to give some more technical details in an answer below.

bla2 12y ago
What do recent cpus do differently?
- alain94040 12y ago
  Just to pick a few statements: by default, loads can fetch stale data . No, not really. everything gets even more vague when Out of Order execution is involved . OOO is the new normal. Not to mention prefetching, which completely destroys any mental model of in-order memory access you could have. Architectures with a weak memory model do the minimum amount of work necessary in the core . I wish. weak memory is very complex. Look up synchronization barriers for an idea of how messy it gets. But again, for software developers, that article is good enough.
  - jblow 12y ago
    Sorry, but you are drastically underestimating the knowledge and experience of the author of the article for no other reason than to try and make yourself look smart, which is failing.
  - stinos 12y ago
    Maybe you are right, maybe you are wrong, but you'll have to come up with a proper and more in-depth explanation or article to convince anyone on HN from your standpoint. Now you are just laying down some buzzwords.
forrestthewoods 12y ago
You have successfully managed to reply to a detailed technical blog post in a manner that provides zero value to anyone and only serves to make you try to sound smarter than the original author. Good job. It'd be great if you could provide value by giving, or linking to, an explanation as to why the post is "not very accurate with respect to recent cpus".

willvarfar 12y ago

If you liked this excellent overview, and you're not too tired of me going on about the new Mill CPU architecture already, you may like that Mill loads specify their retire cycle and represent memory at retire time rather than issue time. The Mill is therefore immune to aliasing races. And this works between cores too!

zxcdw 12y ago
Thanks for your hard work on the Mill CPU. It is truly fascinating to learn about it! I've been waiting for the Pipeline talk for the past week, checking the website few times a day. :) And for those who are interested in this type of thing, here's a talk about the Mill CPU memory system which also touches caches: http://millcomputing.com/docs/memory/ http://millcomputing.com/docs/memory/