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It was my interpretation that "binning" is because of the manufacturing and imperfections in the etching or underlaying wafer cause certain chips to not perform

by caw 12y ago

It was my interpretation that "binning" is because of the manufacturing and imperfections in the etching or underlaying wafer cause certain chips to not perform up to spec. It's not because there's 1.7 Billion of something, but rather because you're drawing at 22nm. The way a processor does math is identical in every single processor, but processor A may result in more heat discharge or higher voltages required than processor B at the same clock rate. Where you get into "it may not compute identically" is the revisions. At Intel at least, going from A0 to B0 means the transistor layout on the wafer changed. Going from B1 to B2 means the wiring layout changed (though the underlaying metal layer remained the same). Again that's a "technically", whether that's followed to a T is something I'm not sure about. Sometimes features are added going between metal revisions.

chrisBob 12y ago
Thanks. It looks like I was wrong. I understood that there was some redundancy build into chips, but that appears to be false. After some more research I think you are right that only the voltage/clock rating vary die to die, and that the transistors must be 100% working. That means that the answer to the OP's question should be that if the data is stored in the same memory location then two chips in adjacent server racks will use the same transistors to do the same math.
- caw 12y ago
  Transistors may not need to be 100% working on 100% of the die to be shipped. If the fault is contained within a subsection, the manufacturer can set fuses to disable portions of the chip. This is generally used to distinguish features between product lines. Processor A could have VT-D failed in manufacturing, so it's fused off and sold as a cheap processor. Processor B could be fully working, but Intel needs to sell more cheap processors, so they intentionally disable VT-D on B. Sony did something similar with shipping Playstation 3s since they couldn't get the yields high enough initially. They disabled 1 SPU of each processor since they could reliably get 7 working ones in manufacturing. Those 8 SPUs are more interchangeable though, they're more like graphics chips in that regard than general x86 CPUs.
- GotAnyMegadeth 12y ago
  There is often redundancy built into the larger internal memories of chips.

by caw 12y ago

chrisBob 12y ago

Thanks. It looks like I was wrong. I understood that there was some redundancy build into chips, but that appears to be false. After some more research I think you are right that only the voltage/clock rating vary die to die, and that the transistors must be 100% working. That means that the answer to the OP's question should be that if the data is stored in the same memory location then two chips in adjacent server racks will use the same transistors to do the same math.

caw 12y ago
Transistors may not need to be 100% working on 100% of the die to be shipped. If the fault is contained within a subsection, the manufacturer can set fuses to disable portions of the chip. This is generally used to distinguish features between product lines. Processor A could have VT-D failed in manufacturing, so it's fused off and sold as a cheap processor. Processor B could be fully working, but Intel needs to sell more cheap processors, so they intentionally disable VT-D on B. Sony did something similar with shipping Playstation 3s since they couldn't get the yields high enough initially. They disabled 1 SPU of each processor since they could reliably get 7 working ones in manufacturing. Those 8 SPUs are more interchangeable though, they're more like graphics chips in that regard than general x86 CPUs.
GotAnyMegadeth 12y ago
There is often redundancy built into the larger internal memories of chips.