Actually 4 cycles for modern cpus. The access time of a cache depends mostly on it's size (wire delay and switching time for the access tree). This means that c

Actually 4 cycles for modern cpus. The access time of a cache depends mostly on it's size (wire delay and switching time for the access tree). This means that cache sizes are always tradeoffs between hit rate and access time. As cpus get better at hiding latency, the access latency is loosened.