4 ms·
As written, that INIT section is really going to limit clock speed. I also don't understand why currentState is double clocked.
by Brashman 12y ago
As written, that INIT section is really going to limit clock speed. I also don't understand why currentState is double clocked.
- scott_wilson46 12y agoIt's not going to limit clock speed, its just not going to work. To write multiple values to different ram locations (considering a ram has at most two ports) would require you to stay in the INIT state for 9 cycles and do something like: INIT: begin if (count == 9) begin next_count == 0; nextState = `EVALUATE; end else next_count == count + 1; case (count) 0: begin ram_wr_addr = count; ram_wr_data = `CMD_LED_ON; ram_wr_en = 1; end 1: begin ram_wr_addr = count; ram_wr_data = `CMD_LOAD_NEXT_TO_ACCU; ram_wr_en = 1; end etc.... end usually you have a ram module that takes an address and some write_data, wr_en, etc rather than accessing the array directly.
- jff 12y agoI think we've come back to "original author doesn't actually know how to write logic, thinks he's writing sequential code" as the core problem
- joelby37 12y agoUsing double-edge clocking usually comes from a misunderstanding about how FPGA timing works. When you look at a waveform in a simulator, it's intuitive to think that you would need to change states at opposite edges to guarantee setup time. The synthesis tools will actually guarantee that setup times are met even if you use the same clock edge, though. Also, the use of a clock divider in this way is bad practice and another trap for beginners. Use clock that are on global clock lines, and use a clock enable to slow things down.