I'm not familiar with Verilog. I wonder if something like this[1] would be a useful tool in this developer's belt. 1: http://www.cs.colby.edu/djskrien/CPUSim/

I'm not familiar with Verilog. I wonder if something like this[1] would be a useful tool in this developer's belt. 1: http://www.cs.colby.edu/djskrien/CPUSim/ http://www.cs.colby.edu/djskrien/CPUSim/