3 ms·
What type of logic are you going to be changing every other week in the Datacenter? What chillingeffect is saying (and I agree) is that this logic should be ru
by orik 12y ago
What type of logic are you going to be changing every other week in the Datacenter?
What chillingeffect is saying (and I agree) is that this logic should be running on the cpu.
- NotAtWork 12y agoExcept that the MS Catapult results seem to suggest that you can get a substantial timing bump without much power overhead by using a second network of FPGAS running concurrently with the CPUS. And in the case of Catapult, they'll be refactoring the algorithm to represent changes to their search feature matching, which is the majority of what they offloaded to FPGAs.
- cfallin 12y agoYes, the Bing example seems to give real-world validation of all this. In general it seems that hardware vs. software fit is orthogonal to concerns such as frequent reconfiguration. Some algorithms simply match hardware well (high concurrency, low-complexity control flow, able to stream through data without complex state). These are often algorithms that do not fit general-purpose CPUs well (cache hierarchy wasted on streaming; lots of control overhead; low core counts relative to FPGA-level parallelism). Some of these algorithms may be for specialized and/or frequently-changing applications such that they should not be burned into an ASIC that will live in a datacenter for 3-5 years.
- caw 12y agoActual chip design needs FPGAs for hardware emulation prior to fabrication. Yes you'll change the logic out on a weekly, daily, or even hourly basis.
- cdcarter 12y agoWell yes, of course, but that's a case where (as mentioned above) the FPGA is a temporary for a final chip.
- sliverstorm 12y agoYes and no. A small ASIC can be prototyped on an FPGA, but FPGA are radically smaller and slower than high end chips.