Well yes, that's why VHDL, Verilog, and the like exists. In those languages, when you "include" a module that is "unsynthesizable", for example the stdio libra

Well yes, that's why VHDL, Verilog, and the like exists. In those languages, when you "include" a module that is "unsynthesizable", for example the stdio library, then the entire program is rendered unsynthesizable and unable to be compiled into logic gates -- but can still be run for simulation purposes.