The consensus seems to be that it's going to be difficult to scale traditional CMOS devices below the 22nm node. At those dimensions, you can't dissipate the he

The consensus seems to be that it's going to be difficult to scale traditional CMOS devices below the 22nm node. At those dimensions, you can't dissipate the heat produced by electrons tunneling through the gate dielectric. Beyond 22nm, it will probably be necessary to use novel gate designs, multiple gates, or start stacking multiple layers of traditional CMOS devices atop one another. There are a lot of ideas right now, but no one knows exactly where the industry will go yet once CMOS is played out. If you want to see where semiconductors are going, the best place to start is the International Technology Roadmap for Semiconductors, (http://www.itrs.net/ http://www.itrs.net/) which the industry compiles every couple of years to help coordinate R&D.