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Don't you get some serious problem with quantum mechanical effects when you have such thin line widths? Is it physically possible to reach 4 nm with current co

• hughprime 17y ago
  Probably. People used to talk about running into quantum mechanics at about the current node, but that was due to tunneling across the gate oxide layer. This is being solved with new high-k dielectric materials. There's probably a whole lot more problems to be solved between now and 4 nm, though. 4 nm is really small. The silicon-silicon lattice spacing is 0.235 nm, so we're really only talking about a few atomic layers. I have no idea how they're going to build 'em that small, and I suspect that Intel's not really sure either.
• gamble 17y ago
  The consensus seems to be that it's going to be difficult to scale traditional CMOS devices below the 22nm node. At those dimensions, you can't dissipate the heat produced by electrons tunneling through the gate dielectric. Beyond 22nm, it will probably be necessary to use novel gate designs, multiple gates, or start stacking multiple layers of traditional CMOS devices atop one another. There are a lot of ideas right now, but no one knows exactly where the industry will go yet once CMOS is played out. If you want to see where semiconductors are going, the best place to start is the International Technology Roadmap for Semiconductors, (http://www.itrs.net/ http://www.itrs.net/) which the industry compiles every couple of years to help coordinate R&D.