> Take existing FPGAs and the synthesized hardware, and some place and route data, and generate cycle perfect simulations. > now cycle accurate hardware simula

> Take existing FPGAs and the synthesized hardware, and some place and route data, and generate cycle perfect simulations. > now cycle accurate hardware simulation is the next target. Can you clarify this? Do you mean, take a 6502 HDL model, place and route it to an FPGA and back-annotate the PaR data into a simulation testbench that runs in an online simulator?