4 ms·
Nice set of articles: flagged as toread. One quick note: with the visual6502 project (http://www.visual6502.org/ http://www.visual6502.org/), and the c-impleme
by zellyn 12y ago
Nice set of articles: flagged as toread.
One quick note: with the visual6502 project (http://www.visual6502.org/ http://www.visual6502.org/), and the c-implementation (https://github.com/mist64/perfect6502 https://github.com/mist64/perfect6502), a fun way to test your emulator timing is to run it in parallel with the gate-level simulation, and compare them. For example, I do this with my golang 6502 emulator: https://github.com/zellyn/go6502/blob/master/tests/compare_test.go https://github.com/zellyn/go6502/blob/master/tests/compare_t...
- paulannesley 12y agoNice project zellyn; I've got one with the same creative repo name: https://github.com/pda/go6502 https://github.com/pda/go6502 ;) Mine currently makes no attempt at being cycle-accurate; it's basically the dev/test environment for a breadboard 6502 computer I'm working on.
- mattgodbolt 12y agoVery nice. I used v6502 a lot as the article shows, but the real fun comes with the cycle-stretching, which AFAICT can't be simulated using v6502.
- zellyn 12y agoHmmm. You should be able to pull the same lines up/down or pause the clock the way the real hardware does it.