The PRAM model itself is interesting. http://en.wikipedia.org/wiki/Parallel_Random_Access_Machine http://en.wikipedia.org/wiki/Parallel_Random_Access_Machine

The PRAM model itself is interesting. http://en.wikipedia.org/wiki/Parallel_Random_Access_Machine http://en.wikipedia.org/wiki/Parallel_Random_Access_Machine > "Similar to the way in which the RAM model neglects practical issues, such as access time to cache memory versus main memory, the PRAM model neglects such issues as synchronization and communication, but provides any (problem-size-dependent) number of processors."