5 ms·

Well, he built his empire on Emitter Coupled Logic. He didn't have the limitations of CMOS to deal with and so parallelism wasn't as necessary for continued c

Well, he built his empire on Emitter Coupled Logic. He didn't have the limitations of CMOS to deal with and so parallelism wasn't as necessary for continued computational power.

weland 13y ago
I...I'm not sure I understand what you mean, but it feels rude to downvote based on it. Can you elaborate on that, please?
- sp332 13y ago
  No one is arguing that parallelism is easier or more convenient than serial processing. (I think.) But clock speeds top out eventually, because power usage goes up with the square of the clock rate and eventually your chip just melts. So the only way to get more performance out of a piece of silicon is to put processors side-by-side.
  - weland 13y ago
    I'm not arguing that either, it's the nonsense about ECL and CMOS above that I can't understand.
    - kjs3 13y ago
      It's not nonsense. By committing to using ECL logic (read: cost is basically no object) Cray didn't need to bother with parallelism to get the best performance possible at the time, and so it was reasonable marketing for him to discount it. If he'd been confined to CMOS (or to a somewhat lesser extent bipolar) logic, he'd have had a very different set of trade-offs to get the performance he needed.
      - weland 13y ago
        > By committing to using ECL logic (read: cost is basically no object) I don't disagree with your assessment of ECL, but I think you're holding the historical account upside down :-). > Cray didn't need to bother with parallelism to get the best performance possible at the time Let's put things into context first: the Cray-1 was a parallel computer. It had vector processing. That's the most trivial kind of computational parallelism (at least from a mathematical point of view) and the Cray-1 had it! Cray not only "bothered" with parallelism, his supercomputers were as parallel as they can get. However, that wasn't new. There had been vector machines before, like CDC's STAR-100. However, one of the reason why they failed to gain traction was precisely the fact they sacrificed serial performance for that. Turns out that's a really bad, bad, bad idea for scientific computing, because 90% of the problems that involve cranking matrices usually involve cranking the same matrices over and over again. So "the best performance possible at the time" (much like today, ironically!) turned out to require not only the parallel processing facilities offered by vector instructions, but also good serial performance, which basically boiled down to SQUEEZE MOAR CYCLES!! Remember, this was still five years before RISC became a thing; it was around the time Cocke began designing the IBM 801 (which only became available in 1980!). At the time, CMOS simply wasn't up to it in that regard. It's not that Cray made a conscious choice to avoid wrestling with CMOS' limitations, there were literally no CMOS logic ICs that moved that fast. Not using CMOS was not a design decision anymore than not using relays was! This was happening at a time when pretty much all serious computing was done with bipolar logic. This was still a good two years away from even the faster companies in the same field (like DEC) abandoned the bipolar logic boat. IBM continued building mainframes with bipolar logic (albeit using TTL, not ECL) well after that (the 4300 was retired in the early 1990s, although I don't know if they were still manufacturing it in TTL; but it definitely was in 1979 when it was introduced!). When CMOS was adopted later on for high-performance computing later on, it wasn't because of the costs! ECL's power dissipation demands made it technically, not economically, unfeasible to make faster logic circuits.
        kjs3 13y ago
        So when shown to be wrong, you redefine the question so you get to be right. Have fun with that.

Well, he built his empire on Emitter Coupled Logic. He didn't have the limitations of CMOS to deal with and so parallelism wasn't as necessary for continued computational power.

weland 13y ago

I...I'm not sure I understand what you mean, but it feels rude to downvote based on it. Can you elaborate on that, please?

sp332 13y ago
No one is arguing that parallelism is easier or more convenient than serial processing. (I think.) But clock speeds top out eventually, because power usage goes up with the square of the clock rate and eventually your chip just melts. So the only way to get more performance out of a piece of silicon is to put processors side-by-side.
- weland 13y ago
  I'm not arguing that either, it's the nonsense about ECL and CMOS above that I can't understand.
  - kjs3 13y ago
    It's not nonsense. By committing to using ECL logic (read: cost is basically no object) Cray didn't need to bother with parallelism to get the best performance possible at the time, and so it was reasonable marketing for him to discount it. If he'd been confined to CMOS (or to a somewhat lesser extent bipolar) logic, he'd have had a very different set of trade-offs to get the performance he needed.
    - weland 13y ago
      > By committing to using ECL logic (read: cost is basically no object) I don't disagree with your assessment of ECL, but I think you're holding the historical account upside down :-). > Cray didn't need to bother with parallelism to get the best performance possible at the time Let's put things into context first: the Cray-1 was a parallel computer. It had vector processing. That's the most trivial kind of computational parallelism (at least from a mathematical point of view) and the Cray-1 had it! Cray not only "bothered" with parallelism, his supercomputers were as parallel as they can get. However, that wasn't new. There had been vector machines before, like CDC's STAR-100. However, one of the reason why they failed to gain traction was precisely the fact they sacrificed serial performance for that. Turns out that's a really bad, bad, bad idea for scientific computing, because 90% of the problems that involve cranking matrices usually involve cranking the same matrices over and over again. So "the best performance possible at the time" (much like today, ironically!) turned out to require not only the parallel processing facilities offered by vector instructions, but also good serial performance, which basically boiled down to SQUEEZE MOAR CYCLES!! Remember, this was still five years before RISC became a thing; it was around the time Cocke began designing the IBM 801 (which only became available in 1980!). At the time, CMOS simply wasn't up to it in that regard. It's not that Cray made a conscious choice to avoid wrestling with CMOS' limitations, there were literally no CMOS logic ICs that moved that fast. Not using CMOS was not a design decision anymore than not using relays was! This was happening at a time when pretty much all serious computing was done with bipolar logic. This was still a good two years away from even the faster companies in the same field (like DEC) abandoned the bipolar logic boat. IBM continued building mainframes with bipolar logic (albeit using TTL, not ECL) well after that (the 4300 was retired in the early 1990s, although I don't know if they were still manufacturing it in TTL; but it definitely was in 1979 when it was introduced!). When CMOS was adopted later on for high-performance computing later on, it wasn't because of the costs! ECL's power dissipation demands made it technically, not economically, unfeasible to make faster logic circuits.
      - kjs3 13y ago
        So when shown to be wrong, you redefine the question so you get to be right. Have fun with that.