You bring up valid questions. I want to clarify some things and see if I can answer... It's not 'most' integrated circuits. Actually, especially with more per

You bring up valid questions. I want to clarify some things and see if I can answer... It's not 'most' integrated circuits. Actually, especially with more personal devices containing sensors, biomaterials, medical devices[Analog/Mixed Signal and low power applications], they have a high content of custom[mixed signal design] that to date is not using hardware description languages. 'Most' applies to digital design, for which hardware description languages do a good job of abstraction. You've actually made a strong point. I think Efabless is creating a connection where the IC designer and customer or system builder will be able to co-create/co-design with a rapid feedback loop online. Similar to what is happening in multinational companies or in the software world, github is a great example. It's making it available/democratizing the selling process easy, tools and access, etc...... kind of like quirky.com. Of course these things are 'hard' for individuals, which is exactly why you can login to the efabless 'maker space' online and they'll give you everything on a platter to design, test, and simulate IC's with a viable chance to get the chip from idea to production especially when you have the customers watch and co-design in the system. Efabless is de-risking .... in 90 seconds you'll be able to login, start designing with real "circuit parameters for a particular process" from one of few known found with design DRC checkers and sign-off processes directly from the foundry. Now that the user has designed it, they can submit it directly to the foundry and within 4 to 8 weeks depending on the process technology and the foundry, they would receive samples of their own designed chip within a certain box and it comes with its own test board that is a basic functional test-board. That being said, efabless would have a marketplace where these designs would be exposed to other IC designers and/or customers to evolve them or provide the feedback necessary to get it into a product if it's the right fit application. Much of unusability is not about the design itself but about the effort to get from a test die to a fully qualified product. They believe that by having that exposure, that efabless as a company would be providing the quality/certification means they can become a very valuable company to the semiconductor industry because a lot more talent and people can contribute to a problem that usually don't get enough attention. In both PCB's and IC designs, having several designs of the same chip is like an insurance policy. You spend more to protect yourself, but you achieve more designs. The cost of failure post-silicon is extremely high. "The cost of failure in IC design".... Who pays for the chip, the software? Can you explain how it costs zero? The smart phones have destroyed any room for additional area or cost that is unnecessary. The required constraints on die area and the sensitivity to the cost on that additional area, has completely changed the way that people think about die area and yield expectations.[defect density yield expectations] Granted, it is not a requirement for all types of applications. FPGAs by definition are not analog. The analog market is $50B market. Greg Buchholz answered your last question head on at the last two sentences. I appreciate you taking the time to write this.