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>So the modern "chip" process has evolved to design it, ship your MVP on FPGAs, if you get sufficient traction you do a two or three metal layer ASIC, if you ge
by GregBuchholz 12y ago
>So the modern "chip" process has evolved to design it, ship your MVP on FPGAs, if you get sufficient traction you do a two or three metal layer ASIC, if you get even more traction you plug in the process design library and do layout for a specific process. Where does efabless fit into that?
I don't know what efabless is all about, but I could see several areas that don't fit your mold. Analog, RF, ultra low power, sensors (optical, etc.), switching power supplies, MEMS, etc..
- ChuckMcM 12y agoThat is a really awesome point. I don't know how you could even begin to cost effectively get the price of designing your own circuit geometries into peoples hands ala kickstarter. Not to mention how to simulate the physics of those devices prior to fabrication.