3 ms·

I should have probably outlined why it's meaningful, or why I'm taking a risk on it. - IC design software as it currently stands has no version control. (I was

I should have probably outlined why it's meaningful, or why I'm taking a risk on it. - IC design software as it currently stands has no version control. (I was shocked at this...) - IC designs are built in a closed box. - There's an absurdly high level of unsellable designs. This occurs because there's no customer feedback loop and you can't predict the direction of the IC market. Additionally, I'm pretty stoked about things like: prefundia.com kickstarter.com Because... they mitigate production risk. The cost of failure in IC design is pretty big. Efabless gives away the software part of it for free to IC designers.

ChuckMcM 12y ago
This doesn't really match my understanding of things, this is what I'm familiar with. IC design software is too loose a term. Most, if not all, integrated circuits are designed these days using a hardware description language (VHDL and Verilog being most popular) and those languages/files have exactly the same level of source code control that any source code does, git, mercurial, CVS, etc. They are just text files, they have a build and a test processes. Further integrated circuits can be collaboratively designed, look at FPGACPU.org as an interesting example. This one is really hard to wrap my head around: CLAIM: There is an absurdly high level of unsalable designs. EVIDENCE: This occurs because there's no customer feedback loop and you can't predict the direction of the IC market. Bad chip designs exist for the same reason that bad software exists, some people just produce bad designs. I think you were trying to argue that there are good designs that didn't get produced, but that is true for any design. So that said lets talk about what is hard. It is hard for me, as an individual, to get a wafer start at a fab. It is hard for me as an individual to generate masks for a specific process. It is hard for me, as an individual, to get the circuit parameters for a particular process and so that I can do both a good layout and can tweak my masks for good yield. It is hard for me, as an individual, to get my processed wafers diced, tested, and packaged. Historically, getting all of those things done to convert a working chip design from simulation to testable parts, has been a few million dollars. And at the end of those millions one has (wafer size / die size ) * layout efficency * process yield * testing yield number of parts. These are divided up into one or more 'bins' (if they are still usable at different frequencies or voltages). And when I divide that number of chips by the amount of money I've spent, I've got a price per chip that has to be something the market will be willing to pay. That is both a lot of hoops, and sitting down for betting one round costs a few million. So what, exactly, is efabless.com de-risking? Unlike circuit boards, you can't easily put several different IC designs on the same chip and expect a fixed yield across them (sort of the OSHPark model). You can do what some folks have done which is buy "excess" capacity on older generation fabs (like Atmel's) and get a discount because you're helping them keep things running, but its still quite expensive. The cost of failure in IC design is nearly zero. Once you've done the simulations you've just burned CPU cycles up to that point. If the process is well characterized there is exactly zero reason for a chip you produce to not work when it comes out the other end. A long time friend from my Intel days remarked that it used to be news if a chip worked the first time, now it is news if it doesn't work the first time you bake it. I can see a challenge that low run rate chips are too expensive for the market they are trying to serve (which is why FPGAs have been growing in leaps and bounds). The original solution, ASICs which are less space efficient than bespoke designs are great for taking an FPGA design into production. So the modern "chip" process has evolved to design it, ship your MVP on FPGAs, if you get sufficient traction you do a two or three metal layer ASIC, if you get even more traction you plug in the process design library and do layout for a specific process. Where does efabless fit into that?
- GregBuchholz 12y ago
  >So the modern "chip" process has evolved to design it, ship your MVP on FPGAs, if you get sufficient traction you do a two or three metal layer ASIC, if you get even more traction you plug in the process design library and do layout for a specific process. Where does efabless fit into that? I don't know what efabless is all about, but I could see several areas that don't fit your mold. Analog, RF, ultra low power, sensors (optical, etc.), switching power supplies, MEMS, etc..
  - ChuckMcM 12y ago
    That is a really awesome point. I don't know how you could even begin to cost effectively get the price of designing your own circuit geometries into peoples hands ala kickstarter. Not to mention how to simulate the physics of those devices prior to fabrication.
- kumarski 12y ago
  You bring up valid questions. I want to clarify some things and see if I can answer... It's not 'most' integrated circuits. Actually, especially with more personal devices containing sensors, biomaterials, medical devices[Analog/Mixed Signal and low power applications], they have a high content of custom[mixed signal design] that to date is not using hardware description languages. 'Most' applies to digital design, for which hardware description languages do a good job of abstraction. You've actually made a strong point. I think Efabless is creating a connection where the IC designer and customer or system builder will be able to co-create/co-design with a rapid feedback loop online. Similar to what is happening in multinational companies or in the software world, github is a great example. It's making it available/democratizing the selling process easy, tools and access, etc...... kind of like quirky.com. Of course these things are 'hard' for individuals, which is exactly why you can login to the efabless 'maker space' online and they'll give you everything on a platter to design, test, and simulate IC's with a viable chance to get the chip from idea to production especially when you have the customers watch and co-design in the system. Efabless is de-risking .... in 90 seconds you'll be able to login, start designing with real "circuit parameters for a particular process" from one of few known found with design DRC checkers and sign-off processes directly from the foundry. Now that the user has designed it, they can submit it directly to the foundry and within 4 to 8 weeks depending on the process technology and the foundry, they would receive samples of their own designed chip within a certain box and it comes with its own test board that is a basic functional test-board. That being said, efabless would have a marketplace where these designs would be exposed to other IC designers and/or customers to evolve them or provide the feedback necessary to get it into a product if it's the right fit application. Much of unusability is not about the design itself but about the effort to get from a test die to a fully qualified product. They believe that by having that exposure, that efabless as a company would be providing the quality/certification means they can become a very valuable company to the semiconductor industry because a lot more talent and people can contribute to a problem that usually don't get enough attention. In both PCB's and IC designs, having several designs of the same chip is like an insurance policy. You spend more to protect yourself, but you achieve more designs. The cost of failure post-silicon is extremely high. "The cost of failure in IC design".... Who pays for the chip, the software? Can you explain how it costs zero? The smart phones have destroyed any room for additional area or cost that is unnecessary. The required constraints on die area and the sensitivity to the cost on that additional area, has completely changed the way that people think about die area and yield expectations.[defect density yield expectations] Granted, it is not a requirement for all types of applications. FPGAs by definition are not analog. The analog market is $50B market. Greg Buchholz answered your last question head on at the last two sentences. I appreciate you taking the time to write this.

ChuckMcM 12y ago

This doesn't really match my understanding of things, this is what I'm familiar with. IC design software is too loose a term. Most, if not all, integrated circuits are designed these days using a hardware description language (VHDL and Verilog being most popular) and those languages/files have exactly the same level of source code control that any source code does, git, mercurial, CVS, etc. They are just text files, they have a build and a test processes. Further integrated circuits can be collaboratively designed, look at FPGACPU.org as an interesting example. This one is really hard to wrap my head around: CLAIM: There is an absurdly high level of unsalable designs. EVIDENCE: This occurs because there's no customer feedback loop and you can't predict the direction of the IC market. Bad chip designs exist for the same reason that bad software exists, some people just produce bad designs. I think you were trying to argue that there are good designs that didn't get produced, but that is true for any design. So that said lets talk about what is hard. It is hard for me, as an individual, to get a wafer start at a fab. It is hard for me as an individual to generate masks for a specific process. It is hard for me, as an individual, to get the circuit parameters for a particular process and so that I can do both a good layout and can tweak my masks for good yield. It is hard for me, as an individual, to get my processed wafers diced, tested, and packaged. Historically, getting all of those things done to convert a working chip design from simulation to testable parts, has been a few million dollars. And at the end of those millions one has (wafer size / die size ) * layout efficency * process yield * testing yield number of parts. These are divided up into one or more 'bins' (if they are still usable at different frequencies or voltages). And when I divide that number of chips by the amount of money I've spent, I've got a price per chip that has to be something the market will be willing to pay. That is both a lot of hoops, and sitting down for betting one round costs a few million. So what, exactly, is efabless.com de-risking? Unlike circuit boards, you can't easily put several different IC designs on the same chip and expect a fixed yield across them (sort of the OSHPark model). You can do what some folks have done which is buy "excess" capacity on older generation fabs (like Atmel's) and get a discount because you're helping them keep things running, but its still quite expensive. The cost of failure in IC design is nearly zero. Once you've done the simulations you've just burned CPU cycles up to that point. If the process is well characterized there is exactly zero reason for a chip you produce to not work when it comes out the other end. A long time friend from my Intel days remarked that it used to be news if a chip worked the first time, now it is news if it doesn't work the first time you bake it. I can see a challenge that low run rate chips are too expensive for the market they are trying to serve (which is why FPGAs have been growing in leaps and bounds). The original solution, ASICs which are less space efficient than bespoke designs are great for taking an FPGA design into production. So the modern "chip" process has evolved to design it, ship your MVP on FPGAs, if you get sufficient traction you do a two or three metal layer ASIC, if you get even more traction you plug in the process design library and do layout for a specific process. Where does efabless fit into that?

GregBuchholz 12y ago
>So the modern "chip" process has evolved to design it, ship your MVP on FPGAs, if you get sufficient traction you do a two or three metal layer ASIC, if you get even more traction you plug in the process design library and do layout for a specific process. Where does efabless fit into that? I don't know what efabless is all about, but I could see several areas that don't fit your mold. Analog, RF, ultra low power, sensors (optical, etc.), switching power supplies, MEMS, etc..
- ChuckMcM 12y ago
  That is a really awesome point. I don't know how you could even begin to cost effectively get the price of designing your own circuit geometries into peoples hands ala kickstarter. Not to mention how to simulate the physics of those devices prior to fabrication.
kumarski 12y ago
You bring up valid questions. I want to clarify some things and see if I can answer... It's not 'most' integrated circuits. Actually, especially with more personal devices containing sensors, biomaterials, medical devices[Analog/Mixed Signal and low power applications], they have a high content of custom[mixed signal design] that to date is not using hardware description languages. 'Most' applies to digital design, for which hardware description languages do a good job of abstraction. You've actually made a strong point. I think Efabless is creating a connection where the IC designer and customer or system builder will be able to co-create/co-design with a rapid feedback loop online. Similar to what is happening in multinational companies or in the software world, github is a great example. It's making it available/democratizing the selling process easy, tools and access, etc...... kind of like quirky.com. Of course these things are 'hard' for individuals, which is exactly why you can login to the efabless 'maker space' online and they'll give you everything on a platter to design, test, and simulate IC's with a viable chance to get the chip from idea to production especially when you have the customers watch and co-design in the system. Efabless is de-risking .... in 90 seconds you'll be able to login, start designing with real "circuit parameters for a particular process" from one of few known found with design DRC checkers and sign-off processes directly from the foundry. Now that the user has designed it, they can submit it directly to the foundry and within 4 to 8 weeks depending on the process technology and the foundry, they would receive samples of their own designed chip within a certain box and it comes with its own test board that is a basic functional test-board. That being said, efabless would have a marketplace where these designs would be exposed to other IC designers and/or customers to evolve them or provide the feedback necessary to get it into a product if it's the right fit application. Much of unusability is not about the design itself but about the effort to get from a test die to a fully qualified product. They believe that by having that exposure, that efabless as a company would be providing the quality/certification means they can become a very valuable company to the semiconductor industry because a lot more talent and people can contribute to a problem that usually don't get enough attention. In both PCB's and IC designs, having several designs of the same chip is like an insurance policy. You spend more to protect yourself, but you achieve more designs. The cost of failure post-silicon is extremely high. "The cost of failure in IC design".... Who pays for the chip, the software? Can you explain how it costs zero? The smart phones have destroyed any room for additional area or cost that is unnecessary. The required constraints on die area and the sensitivity to the cost on that additional area, has completely changed the way that people think about die area and yield expectations.[defect density yield expectations] Granted, it is not a requirement for all types of applications. FPGAs by definition are not analog. The analog market is $50B market. Greg Buchholz answered your last question head on at the last two sentences. I appreciate you taking the time to write this.