5 ms·

Always great to see new developments in HDLs. It seems there is no synthesis (which is to be expected without vendor support). With 'limited' conversion to VHD

by ioseph 12y ago

Always great to see new developments in HDLs. It seems there is no synthesis (which is to be expected without vendor support). With 'limited' conversion to VHDL/Verilog, I wonder how useful this is for actual implementation. Also from the site I couldn't find any mention of higher level functionality such as generics, etc.

mattip 12y ago
MyHDL is not bad for quick prototyping. The main problem I had was using vendor-supplied libraries in simulation, I needed to completely model the vendor block (timing and input-output) which is quite error prone. OTOH, one of the nice things is the ease of moving from a numpy model of the system to RTL. And using PyPy for running simulations really makes MyHDL hum along quickly [0] [0] http://old.myhdl.org/doku.php/performance http://old.myhdl.org/doku.php/performance
int19h 12y ago
SystemC is the C++ equivalent that's been around for a long time. For a project I was working on, I used SystemC just for system-level modelling, it didn't bother me that I couldn't synthesize. To achieve decent clock-rates it would have been a good idea to reimplement the whole thing in "native" Verilog anyway (though my project didn't get that far). What SystemC provided me with is a way to sanity-check my model at the "transaction" level. Pretty cool to see this, and going forward as a roadmap there is much they could borrow from SystemC.
- jandecaluwe 12y ago
  MyHDL is implemented as a minimalistic pure Python library, which basically means that you can use Python features for modeling - pretty powerful. In addition, it supports conversion of a language subset, so that you can also use it as a synthesizable RTL language. The latter feature is absent from SystemC.
jandecaluwe 12y ago
MyHDL has been and is being used for production designs. For parametrizability, you have the full Python power at your disposal. This is also true for conversion, because conversion happens after elaboration of the design.

by ioseph 12y ago

mattip 12y ago

MyHDL is not bad for quick prototyping. The main problem I had was using vendor-supplied libraries in simulation, I needed to completely model the vendor block (timing and input-output) which is quite error prone. OTOH, one of the nice things is the ease of moving from a numpy model of the system to RTL. And using PyPy for running simulations really makes MyHDL hum along quickly [0] [0] http://old.myhdl.org/doku.php/performance http://old.myhdl.org/doku.php/performance

int19h 12y ago

SystemC is the C++ equivalent that's been around for a long time. For a project I was working on, I used SystemC just for system-level modelling, it didn't bother me that I couldn't synthesize. To achieve decent clock-rates it would have been a good idea to reimplement the whole thing in "native" Verilog anyway (though my project didn't get that far). What SystemC provided me with is a way to sanity-check my model at the "transaction" level. Pretty cool to see this, and going forward as a roadmap there is much they could borrow from SystemC.

jandecaluwe 12y ago
MyHDL is implemented as a minimalistic pure Python library, which basically means that you can use Python features for modeling - pretty powerful. In addition, it supports conversion of a language subset, so that you can also use it as a synthesizable RTL language. The latter feature is absent from SystemC.

jandecaluwe 12y ago

MyHDL has been and is being used for production designs. For parametrizability, you have the full Python power at your disposal. This is also true for conversion, because conversion happens after elaboration of the design.